Results 1-62 of 62 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)TypescopusWOSFulltext/Archive link
12017Joint sequence learning and cross-modality convolution for 3D biomedical segmentationTseng, K.-L.; Lin, Y.-L.; Hsu, W.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper360
22017Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation.Tseng, Kuan-Lun; Lin, Yen-Liang; Hsu, Winston H.; Huang, Chung-Yang; CHUNG-YANG HUANG journal article
32016Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approachYeh, Y.-F.; Lin, S.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG journal article00
42016Automatic abstraction refinement of TR for PDRFan, K.; Yang, M.-J.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper20
52015NBM-T-BBX-OS01, Semisynthesized from Osthole, Induced G1 Growth Arrest through HDAC6 Inhibition in Lung Cancer CellsPai, Jih-Tung; Hsu, Chia-Yun; Hua, Kuo-Tai; Yu, Sheng-Yung; Huang, Chung-Yang; Chen, Chia-Nan; Liao, Chiung-Ho; Weng, Meng-Shih; CHUNG-YANG HUANG journal article88
62014Adaptive interpolation-based model checkingLai, C.-Y.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG conference paper00
72014A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model CheckingWu, Cheng-Yin; Wu, Chi-An; Lai, Chien-Yu; Huang, Chung-Yang R.; CHUNG-YANG HUANG journal article43
82014A high-throughput and arbitrary-distribution pattern generator for the constrained random verificationWu, B.-H.; Yang, C.-J.; Huang, C.-Y.; CHUNG-YANG HUANG journal article44
92013Conquering the scheduling alternative explosion problem of SystemC symbolic simulationChou, C.-N.; Chu, C.-K.; Huang, C.-Y.R.; CHUNG-YANG HUANG conference paper70
102013Match and replace: A functional ECO engine for multierror circuit rectificationHuang, S.-L.; Lin, W.-H.; Huang, P.-K.; Huang, C.-Y.; CHUNG-YANG HUANG journal article149
112013A counterexample-guided interpolant generation algorithm for SAT-based model checkingWu, C.-Y.; Wu, C.-A.; Lai, C.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper40
122013A robust constraint solving framework for multiple constraint sets in constrained random verificationWu, B.-H.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper10
132013An ultrasynchronization checking method with trace-driven simulation for fast and accurate MPSoC virtual platform simulationYeh, Y.-F.; Lin, H.-C.; Huang, C.-Y.; CHUNG-YANG HUANG journal article11
142012A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraintsTsai, S.-H.; Li, M.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper00
152012Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction.Tang, Kai-Fu; Huang, Po-Kai; Chou, Chun-Nan; Huang, Chung-Yang; CHUNG-YANG HUANG conference paper00
162012Symbolic model checking on SystemC designsChou, C.-N.; Ho, Y.-S.; Hsieh, C.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper290
172012A robust general constrained random pattern generator for constraints with variable ordering.Wu, Bo-Han; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG conference paper40
182012QuteRTL: Towards an open source framework for RTL design synthesis and verificationYeh, H.-H.; Wu, C.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG conference paper30
192011Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking MethodCHUNG-YANG HUANG conference paper1
202011SoC HW/SW Verification and ValidationCHUNG-YANG HUANG conference paper330
212011A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing OptimizationShao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG conference paper130
222011Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniquesWu, B.-H.; Yang, C.-J.; Tso, C.-C.; Huang, C.-Y.R.; CHUNG-YANG HUANG conference paper60
232011Property-specific sequential invariant extraction for SAT-based unbounded model checkingYeh, H.-H.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG conference paper10
242011Match and replace - A functional ECO engine for multi-error circuit rectification.Huang, Shao-Lun; Lin, Wei-Hsun; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG conference paper60
252011Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG conference paper00
262011Using SAT-based Craig interpolation to enlarge clock gating functions.Lin, Ting-Hao; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG conference paper70
272011Interpolation-based incremental ECO synthesis for multi-error logic rectification.Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG conference paper210
282010Formal Deadlock Checking on High-Level SystemC DesignsCHUNG-YANG HUANG conference paper90
292010A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation TechniquesBo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG conference paper320
302010To SAT or Not to SAT: Scalable Exploration of Functional DependencyJiang, J.-H.R.; CHUNG-YANG HUANG ; JIE-HONG JIANG ; Lee, Chih-Chun; Mishchenko, A.; Huang, Chung-Yang journal article2116
312010Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and SchedulingCHUNG-YANG HUANG conference paper30
322010A Unified Multi-Corner Multi-Mode Static Timing Analysis EngineChin-Chia Nien; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG conference paper50
332010Automatic Constraint Generation for Guided Random SimulationHu-Hsi Yeh; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG conference paper80
342009Interpolant Generation without Constructing Resolution GraphCHUNG-YANG HUANG conference paper3
352009A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input TransitionsShih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG conference paper6
362009Electronic Design Automation: Synthesis, Verification, and TestCHUNG-YANG HUANG book
372009Fundamentals of AlgorithmsHuang, C.-Y.; Lai, C.-Y.; Cheng, K.T.; CHUNG-YANG HUANG book chapter10
382009A false-path aware formal static timing analyzer considering simultaneous input transitions.Tsai, Shihheng; Huang, Chung-Yang; CHUNG-YANG HUANG conference paper00
392009SAT-controlled redundancy addition and removal: a novel circuit restructuring techniqueWu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang conference paper60
402009Interpolant generation without constructing resolution graph.Hsu, Chih-Jen; Huang, Shao-Lun; Wu, Chi-An; Huang, Chung-Yang; CHUNG-YANG HUANG conference paper30
412008Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual SynchronizationCHUNG-YANG HUANG conference paper10
422008Improving Constant-Coefficient Multiplier Verification by Partial Product IdentificationCHUNG-YANG HUANG conference paper50
432008Characterisation of Taiwanese propolis collected from different locations and seasonsChen, Yue-Wen; Wu, Shiao-Wen; Ho, Kai-Kuang; Lin, Shih-Bin; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG journal article3534
442007Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT SolvingCHUNG-YANG HUANG ; JIE-HONG JIANG conference paper470
452007QuteIP: An IP Qualification Framework for System on ChipCHUNG-YANG HUANG conference paper10
462007兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(2/3)黃鐘揚 report
472007FSTA:正規靜態時序分析技術(II)黃鐘揚 report
482007兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(3/3)黃鐘揚 report
492007QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit StructureCHUNG-YANG HUANG conference paper110
502007Propolin G, a prenylflavanone, isolated from Taiwanese propolis, induces caspase-dependent apoptosis in brain cancer cellsHuang, Wei-Jan; Huang, Chih-Hsiang; Wu, Chia-Li; Lin, Jen-Kun; Chen, Yue-Wen; Lin, Chun-Liang; Chuang, Shuang-En; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG journal article5549
512006Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification VectorsCHUNG-YANG HUANG patent
522003Non-Assignable Signal Support During Formal Verification Of Circuit DesignsCHUNG-YANG HUANG patent
532003A Circuit SAT Solver with Signal Correlation Guided LearningFeng Lu; Li-C. Wang; K-T. Cheng,; Ric C-Y. Huang; CHUNG-YANG HUANG conference paper810
542001An Analysis of ATPG and SAT algorithms for Formal VerificationG. Parthasarathy; K-T. Cheng; C-Y Huang; CHUNG-YANG HUANG conference paper170
552001Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property CheckingCHUNG-YANG HUANG journal article3831
562000AQUILA: An equivalence checking system for large sequential designsHuang, S.-Y.; Cheng, K.-T.; Chen, K.-C.; Huang, C.-Y.; Brewer, F.; CHUNG-YANG HUANG journal article3623
572000Static property checking using ATPG vs. BDD techniques.Huang, Chung-Yang; Yang, Bwolen; Tsai, Huan-Chih; Cheng, Kwang-Ting; CHUNG-YANG HUANG conference paper00
582000Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques.Huang, Chung-Yang; Cheng, Kwang-Ting; CHUNG-YANG HUANG conference paper350
591999Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification VectorsCHUNG-YANG HUANG conference paper
601998A New Extended Finite State Machine (EFSM) Model for RTL Design VerificationR.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG conference paper
611998Libra - A Library-Independent Framework for Post-Layout Performance OptimizationCHUNG-YANG HUANG conference paper9
621998LIBRA - a library-independent framework for post-layout performance optimization.Huang, Chung-Yang; Wang, Yucheng; Cheng, Kwang-Ting; CHUNG-YANG HUANG conference paper90