第 1 到 61 筆結果,共 61 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2021 | Compatible Equivalence Checking of X-Valued Circuits | Wang Y.-N; Luo Y.-R; Chien P.-C; Wang P.-L; Wang H.-R; Lin W.-H; JIE-HONG JIANG ; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2 | 2017 | Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. | Tseng, Kuan-Lun; Lin, Yen-Liang; WINSTON HSU ; CHUNG-YANG HUANG | CoRR | 124 | ||
3 | 2017 | Joint sequence learning and cross-modality convolution for 3D biomedical segmentation | Tseng K.-L.; Lin Y.-L.; Hsu W. ; WINSTON HSU ; CHUNG-YANG HUANG | 30th IEEE Conference on Computer Vision and Pattern Recognition | 123 | 0 | |
4 | 2016 | Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach | Yeh, Yu-Fu; Lin, Shu-Yen; SHU-YEN LIN ; CHUNG-YANG HUANG | Journal of the Chinese Institute of Engineers | 0 | 0 | |
5 | 2016 | Automatic abstraction refinement of TR for PDR | Fan, K.; Yang, M.-J.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
6 | 2015 | NBM-T-BBX-OS01, Semisynthesized from Osthole, Induced G1 Growth Arrest through HDAC6 Inhibition in Lung Cancer Cells | Pai, Jih-Tung; Hsu, Chia-Yun; Hua, Kuo-Tai; Yu, Sheng-Yung; Huang, Chung-Yang; Chen, Chia-Nan; Liao, Chiung-Ho; CHUNG-YANG HUANG | Molecules | 18 | 17 | |
7 | 2014 | A high-throughput and arbitrary-distribution pattern generator for the constrained random verification | Wu, B.-H.; Yang, C.-J.; Huang, C.-Y.; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 7 | 7 | |
8 | 2014 | Adaptive interpolation-based model checking | Lai, C.-Y.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
9 | 2014 | A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking | Wu, Cheng-Yin; Wu, Chi-An; Lai, Chien-Yu; Huang, Chung-Yang R.; CHUNG-YANG HUANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 4 | |
10 | 2013 | A counterexample-guided interpolant generation algorithm for SAT-based model checking | Wu, C.-Y.; Wu, C.-A.; Lai, C.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | 4 | 0 | |
11 | 2013 | An ultrasynchronization checking method with trace-driven simulation for fast and accurate MPSoC virtual platform simulation | Yeh, Y.-F.; Lin, H.-C.; Huang, C.-Y.; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 1 | |
12 | 2013 | Conquering the scheduling alternative explosion problem of SystemC symbolic simulation | Chou, C.-N.; Chu, C.-K.; Huang, C.-Y.R.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 11 | 0 | |
13 | 2013 | Match and replace: A functional ECO engine for multierror circuit rectification | Huang, S.-L.; Lin, W.-H.; Huang, P.-K.; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 12 | |
14 | 2013 | A robust constraint solving framework for multiple constraint sets in constrained random verification | Wu, B.-H.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | 4 | 0 | |
15 | 2012 | Symbolic model checking on SystemC designs | Chou, C.-N.; Ho, Y.-S.; Hsieh, C.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | 36 | 0 | |
16 | 2012 | A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints | Tsai, S.-H.; Li, M.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | 0 | |
17 | 2012 | A robust general constrained random pattern generator for constraints with variable ordering. | Wu, Bo-Han; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | 4 | 0 | |
18 | 2012 | QuteRTL: Towards an open source framework for RTL design synthesis and verification | Yeh, H.-H.; Wu, C.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | 5 | 0 | |
19 | 2012 | Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. | Tang, Kai-Fu; Huang, Po-Kai; Chou, Chun-Nan; Huang, Chung-Yang; CHUNG-YANG HUANG | 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012 | 0 | 0 | |
20 | 2011 | Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method | Yu-Fu Yeh; Chung-Yang (Ric) Huang; Chi-An Wu; Hsin-Cheng Lin; CHUNG-YANG HUANG | ACM/IEEE Design, Automation, and Test in Europe (DATE) conference | 1 | ||
21 | 2011 | SoC HW/SW Verification and Validation | CHUNG-YANG HUANG ; Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 39 | 0 | |
22 | 2011 | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization | Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 13 | 0 | |
23 | 2011 | Interpolation-based incremental ECO synthesis for multi-error logic rectification. | Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 25 | 0 | |
24 | 2011 | Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques | Wu, B.-H.; Yang, C.-J.; Tso, C.-C.; Huang, C.-Y.R.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 7 | 0 | |
25 | 2011 | Property-specific sequential invariant extraction for SAT-based unbounded model checking | Yeh, H.-H.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
26 | 2011 | Using SAT-based Craig interpolation to enlarge clock gating functions. | Lin, Ting-Hao; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 7 | 0 | |
27 | 2011 | Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. | Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG | Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011 | 0 | 0 | |
28 | 2010 | Formal Deadlock Checking on High-Level SystemC Designs | Chun-Nan Chou; Chang-Hong Hsu; Yueh-Tung Chao; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 10 | 0 | |
29 | 2010 | A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques | Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 36 | 0 | |
30 | 2010 | To SAT or Not to SAT: Scalable Exploration of Functional Dependency | Jie-Hong R. Jiang; Chih-Chun Lee; Alan Mishchenko; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE Transactions on Computers (TCOMP) | 23 | 18 | |
31 | 2010 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling | Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 4 | 0 | |
32 | 2010 | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine | Chin-Chia Nien; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 9 | 0 | |
33 | 2010 | Automatic Constraint Generation for Guided Random Simulation | Hu-Hsi Yeh; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 9 | 0 | |
34 | 2009 | A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions | Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM Design Automation Conference (DAC) | 7 | ||
35 | 2009 | Electronic Design Automation: Synthesis, Verification, and Test | L-T. Wang; K-T. Cheng; Y-W. Chang; C-Y. Huang; et. al.; CHUNG-YANG HUANG | ||||
36 | 2009 | Interpolant generation without constructing resolution graph. | Hsu, Chih-Jen; Huang, Shao-Lun; Wu, Chi-An; CHUNG-YANG HUANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 3 | 0 | |
37 | 2009 | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique | Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang | Asia and South Pacific Design Automation Conference, 2009. ASP-DAC | 7 | 0 | |
38 | 2009 | Fundamentals of Algorithms | CHUNG-YANG HUANG ; Lai, C.-Y.; Cheng, K.T. | Electronic Design Automation | 13 | 0 | |
39 | 2009 | A false-path aware formal static timing analyzer considering simultaneous input transitions. | Tsai, Shihheng; Huang, Chung-Yang; CHUNG-YANG HUANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 0 | 0 | |
40 | 2008 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization | Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | International SoC Design Conference (ISoCC) | 1 | 0 | |
41 | 2008 | Improving Constant-Coefficient Multiplier Verification by Partial Product Identification | Chao-Yue (Colby) Lai; CHUNG-YANG HUANG ; Kei-Yong Khoo | Design Automation and Test in Europe (DATE) | 6 | 0 | |
42 | 2008 | Characterisation of Taiwanese propolis collected from different locations and seasons | Chen, Yue-Wen; Wu, Shiao-Wen; Ho, Kai-Kuang; Lin, Shih-Bin; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG | Journal of the Science of Food and Agriculture | 44 | 42 | |
43 | 2007 | Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving | Chih-Chun Lee; Jie-Hong R. Jiang; Chung-Yang Huang; Alan Mishchenko; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07) | 50 | 0 | |
44 | 2007 | QuteIP: An IP Qualification Framework for System on Chip | Hsing-Chih Hung; Chi-Wen Chang; Tin-Hao Lin; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE SoC Conference (SOCC) | 1 | 0 | |
45 | 2007 | 兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(3/3) | 黃鐘揚 | ||||
46 | 2007 | FSTA:正規靜態時序分析技術(II) | 黃鐘揚 | ||||
47 | 2007 | 兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(2/3) | 黃鐘揚 | ||||
48 | 2007 | QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure | Chi-An Wu; Ting-Hao Lin; Chih-Chun Lee; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | Design Automation and Test in Europe (DATE) Conference | 17 | 0 | |
49 | 2007 | Propolin G, a prenylflavanone, isolated from Taiwanese propolis, induces caspase-dependent apoptosis in brain cancer cells | Huang, Wei-Jan; Huang, Chih-Hsiang; Wu, Chia-Li; Lin, Jen-Kun; Chen, Yue-Wen; Lin, Chun-Liang; Chuang, Shuang-En; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG | Journal of Agricultural and Food Chemistry | 73 | 65 | |
50 | 2006 | Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors | Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ||||
51 | 2003 | Non-Assignable Signal Support During Formal Verification Of Circuit Designs | Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ||||
52 | 2003 | A Circuit SAT Solver with Signal Correlation Guided Learning | Feng Lu; Li-C. Wang; K-T. Cheng,; Ric C-Y. Huang; CHUNG-YANG HUANG | Design Automation & Test Conference | 96 | 0 | |
53 | 2001 | An Analysis of ATPG and SAT algorithms for Formal Verification | G. Parthasarathy; K-T. Cheng; C-Y Huang; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | 19 | 0 | |
54 | 2001 | Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 38 | 31 | |
55 | 2000 | Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. | Huang, Chung-Yang; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 35 | 0 | |
56 | 2000 | AQUILA: An equivalence checking system for large sequential designs | Huang, S.-Y.; Cheng, K.-T.; Chen, K.-C.; Huang, C.-Y.; Brewer, F.; CHUNG-YANG HUANG | IEEE Transactions on Computers | 37 | 24 | |
57 | 2000 | Static property checking using ATPG vs. BDD techniques. | Huang, Chung-Yang; Yang, Bwolen; Tsai, Huan-Chih; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | 0 | 0 | |
58 | 1999 | Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
59 | 1998 | A New Extended Finite State Machine (EFSM) Model for RTL Design Verification | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
60 | 1998 | Libra - A Library-Independent Framework for Post-Layout Performance Optimization | R.C.-Y. Huang; Y. Wang; K.-T. Cheng; CHUNG-YANG HUANG | International Symposium on Physical Design | 9 | ||
61 | 1998 | LIBRA - a library-independent framework for post-layout performance optimization. | Huang, Chung-Yang; Wang, Yucheng; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998 | 10 | 0 |