第 1 到 5 筆結果,共 5 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2014 | A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking | Wu, Cheng-Yin; Wu, Chi-An; Lai, Chien-Yu; CHUNG-YANG HUANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | ||
2 | 2011 | Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. | Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG | Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011 | |||
3 | 2011 | Interpolation-based incremental ECO synthesis for multi-error logic rectification. | Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | |||
4 | 2009 | Interpolant generation without constructing resolution graph. | Hsu, Chih-Jen; Huang, Shao-Lun; Wu, Chi-An; CHUNG-YANG HUANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 3 | 0 | |
5 | 2009 | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique | Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang | Asia and South Pacific Design Automation Conference, 2009. ASP-DAC | 7 | 0 |