Publications


Results 1-158 of 158 (Search time: 0.006 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12023Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse ProcessingWei, Ming Liang; Yayla, Mikail; Ho, Shu Yin; Chen, Jian Jia; Amrouch, Hussam; CHIA-LIN YANG IEEE Transactions on Circuits and Systems I: Regular Papers
22023Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical IsometryChen, Xuan Jun; Kuan, Cynthia; CHIA-LIN YANG Proceedings - Design Automation Conference
32023Tensor Movement Orchestration in Multi-GPU Training SystemsLin, Shao Fu; Chen, Yi Jung; Cheng, Hsiang Yun; CHIA-LIN YANG Proceedings - International Symposium on High-Performance Computer Architecture00
42023Reliable Brain-inspired AI Accelerators using Classical and Emerging MemoriesYayla, Mikail; Thomann, Simon; Islam, Md Mazharul; Wei, Ming Liang; Ho, Shu Yin; Aziz, Ahmedullah; CHIA-LIN YANG ; Chen, Jian Jia; Amrouch, HussamProceedings of the IEEE VLSI Test Symposium
52022A Forward Speculative Interference AttackCHIA-LIN YANG ; Vetter, RonComputer00
62022DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN AcceleratorsLin, Wei Ting; Cheng, Hsiang Yun; CHIA-LIN YANG ; Lin, Meng Yao; Lien, Kai; Hu, Han Wen; Chang, Hung Sheng; Li, Hsiang Pang; Chang, Meng Fan; Tsou, Yen Ting; Nien, Chin FuACM Transactions on Embedded Computing Systems31
72022Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid LoggingDong, Nai Jia; Cheng, Hsiang Yun; CHIA-LIN YANG ; Lin, Bo Rong; Li, Hsiang PangProceedings - 2022 IEEE 11th Non-Volatile Memory Systems and Applications Symposium, NVMSA 202200
82022RM-SSD: In-Storage Computing for Large-Scale Recommendation InferenceSun X; Wan H; Li Q; CHIA-LIN YANG ; TEI-WEI KUO ; Xue C.J.Proceedings - International Symposium on High-Performance Computer Architecture90
92022Efficient Bad Block Management with Cluster SimilarityYen J.-N; Hsieh Y.-C; Chen C.-Y; Chen T.-Y; CHIA-LIN YANG ; Cheng H.-Y; Luo Y.Proceedings - International Symposium on High-Performance Computer Architecture20
102022PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model SupportLin C.-H; Lin S.-F; Chen Y.-J; Jenp E.-Y; CHIA-LIN YANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
112022This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN AcceleratorTsou Y.-T; Chent K.-H; CHIA-LIN YANG ; Cheng H.-Y; Chen J.-J; Tsai D.-Y.Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
122021Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through BinarizationWei M.-L; Yayla M; Ho S.-Y; Chen J.-J; Yang C.-L; Amrouch H.; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD50
132021Future Computing Platform Design: A Cross-Layer Design ApproachCheng H.-Y; Wu C.-F; Hakert C; Chen K.-H; Chang Y.-H; Chen J.-J; Yang C.-L; CHIA-LIN YANG ; TEI-WEI KUO Proceedings -Design, Automation and Test in Europe, DATE60
142021Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile SynapsesWei M.-L; Amrouch H; Sung C.-L; Lue H.-T; Yang C.-L; Wang K.-C; Lu C.-Y.; CHIA-LIN YANG IEEE International Reliability Physics Symposium Proceedings50
152021Analyzing the Interplay between Random Shuffling and Storage Devices for Efficient Machine LearningKe Z.-L; Cheng H.-Y; Yang C.-L; Huang H.-W.; CHIA-LIN YANG Proceedings - 2021 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 202100
162021A dense tensor accelerator with data exchange mesh for DNN and vision workloadsLin Y.-S; Chen W.-C; Yang C.-L; SHAO-YI CHIEN ; CHIA-LIN YANG Proceedings - IEEE International Symposium on Circuits and Systems10
172020FlashEmbedding: Storing embedding tables in SSD for large-scale recommender systemsWan H; Sun X; Cui Y; CHIA-LIN YANG ; TEI-WEI KUO ; Xue C.J.APSys 2021 - Proceedings of the 12th ACM SIGOPS Asia-Pacific Workshop on Systems80
182020Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networksZheng, Q.; Wang, Z.; Feng, Z.; Yan, B.; Cai, Y.; Huang, R.; Chen, Y.; Yang, C.-L.; Li, H.H.; CHIA-LIN YANG Proceedings - Design Automation Conference190
192019The impact of emerging technologies on architectures and system-level management: Invited paperHenkel, J.; Hu, X.S.; Cheng, H.-Y.; Yang, C.-L.; Amrouch, H.; Rapp, M.; Salamin, S.; Reis, D.; Gao, D.; Yin, X.; Niemier, M.; Zhuo, C.; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD10
202019Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge DevicesLee, C.-I.; Lin, M.-Y.; Yang, C.-L.; Chen, Y.-K.; CHIA-LIN YANG Proceedings - International Conference on Image Processing, ICIP80
212019Sparse ReRAM engine: Joint exploration of activation and weight sparsity in compressed neural networksYang, T.-H.; Cheng, H.-Y.; Yang, C.-L.; Tseng, I.-C.; Hu, H.-W.; Chang, H.-S.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings - International Symposium on Computer Architecture1150
222019Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2019, Hangzhou, China, August 18-21, 201920
232018The impact of 2016 guideline on clinical practice for the management of hospital-acquired and ventilator-associated pneumonia in TaiwanYang, Chia-Lin; Chen, Yen-Fu; Lin, Chi-Ying; CHIA-LIN YANG European Respiratory Journal00
242018DL-RSIM: A simulation framework to enable reliable ReRAM-based accelerators for deep learningLin, M.-Y.; Cheng, H.-Y.; Lin, W.-T.; Yang, T.-H.; Tseng, I.-C.; Yang, C.-L.; Hu, H.-W.; Chang, H.-S.; Li, H.-P.; CHIA-LIN YANG ; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD520
252018Active forwarding: Eliminate IOMMU address translation for accelerator-rich architecturesFu, H.-C.; Wang, P.-H.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings - Design Automation Conference10
262017Message from the general co-chairsGarrett, D.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings of the International Symposium on Low Power Electronics and Design00
272017Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level ObjectivesChang, C.-W.; Chen, G.-Y.; Chen, Y.-J.; Yeh, C.-W.; Eng, P.Y.; Cheung, A.; Yang, C.-L.; CHIA-LIN YANG IEEE Transactions on Computers1513
282017Enabling fast preemption via dual-kernel support on GPUsShieh, L.-W.; Chen, K.-C.; Fu, H.-C.; Wang, P.-H.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC20
292017Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED)Garrett, D.; CHIA-LIN YANG ; CHIA-LIN YANG IEEE Design and Test00
302017Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating ApproachLai, C.-H.; Zhao, J.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings - Design Automation Conference110
312017Improving GPGPU Performance via Cache Locality Aware Thread Block SchedulingChen, Li-Jhan; Cheng, Hsiang-Yun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG Ieee Computer Architecture Letters08
322017Analyzing opencl 2.0 workloads using a heterogeneous CPU-GPU simulatorWang, L.; Tsai, R.-W.; Wang, S.-C.; Chen, K.-C.; Wang, P.-H.; Cheng, H.-Y.; Lee, Y.-C.; Shu, S.-J.; Yang, C.-C.; Hsu, M.-Y.; Kan, L.-C.; Lee, C.-L.; Yu, T.-C.; Peng, R.-D.; Yang, C.-L.; Hwang, Y.-S.; Lee, J.-K.; Tsao, S.-L.; CHIA-LIN YANG ; MING OUHYOUNG ISPASS 2017 - IEEE International Symposium on Performance Analysis of Systems and Software30
332016Improving Read Performance of NAND Flash SSDs by Exploiting Error LocalityLiu, R.-S.; Chuang, M.-Y.; Yang, C.-L.; Li, C.-H.; Ho, K.-C.; Li, H.-P.; CHIA-LIN YANG IEEE Transactions on Computers 2118
342016Message from the Program Co-ChairsYang, C.-L.; Garrett, D.; CHIA-LIN YANG Proceedings of the International Symposium on Low Power Electronics and Design00
352016Latency sensitivity-based cache partitioning for heterogeneous multi-core architectureWang, P.-H.; Li, C.-H.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings - Design Automation Conference130
362016A hybrid DRAM/PCM buffer cache architecture for smartphones with QoS considerationLin, Y.-J.; Yang, C.-L.; Li, H.-P.; Wang, C.-Y.M.; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems65
372016Message from the general chairsHsu, W.C.; CHIA-LIN YANG ; WEI-CHUNG HSU Proceedings of the Annual International Symposium on Microarchitecture, MICRO00
382016MCSSim: A memory channel storage simulatorChen, R.; Shao, Z.; Yang, C.-L.; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
392016Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3D-Stacked DRAMs for Efficient Thermal ControlChen, Yi-Jung; Yang, Chia-Lin; Lin, Pin-Sheng; Lu, Yi-Chang; CHIA-LIN YANG Applied Computing Review50
402015SECRET: A selective error correction framework for refresh energy reduction in DRAMsLin, C.-H.; Shen, D.-Y.; Chen, Y.-J.; Yang, C.-L.; Wang, C.-Y.M.; CHIA-LIN YANG ACM Transactions on Architecture and Code Optimization 88
412015Fine-grained write scheduling for PCM performance improvement under write power budget.Lai, Chun-Hao; Yu, Shun-Chih; Yang, Chia-Lin; CHIA-LIN YANG ; CHIA-LIN YANG IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 201560
422015Improving DRAM latency with dynamic asymmetric subarrayLu, S.-L.; Lin, Y.-C.; CHIA-LIN YANG ; CHIA-LIN YANG Annual International Symposium on Microarchitecture370
432015A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.Lin, Ye-Jyun; Yang, Chia-Lin; Li, Hsiang-Pang; CHIA-LIN YANG ; CHIA-LIN YANG IEEE Non-Volatile Memory System and Applications Symposium, NVMSA 2015, Hong Kong, China, August 19-21, 2015140
442015System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware ApproachLin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; CHIA-LIN YANG ; CHIH-WEN HSUEH Acm Transactions on Embedded Computing Systems43
452014NVM Duet: Unified working memory and persistent store architectureLiu, R.-S.; Shen, D.-Y.; Yang, C.-L.; Yu, S.-C.; CHIA-LIN YANG ; CHIA-LIN YANG International Conference on Architectural Support for Programming Languages and Operating Systems9565
462014Full system simulation framework for integrated CPU/GPU architectureWang, P.-H.; Liu, G.-H.; Yeh, J.-C.; Chen, T.-M.; Huang, H.-Y.; Yang, C.-L.; Liu, S.-L.; CHIA-LIN YANG ; CHIA-LIN YANG Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test60
472014Guest editors' introduction: Cloud computing for embedded systemsDimitrov, M.; Lu, Y.-H.; CHIA-LIN YANG ; CHIA-LIN YANG IEEE Design and Test22
482014EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; CHIA-LIN YANG ; CHIA-LIN YANG The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014200
492013Thermal coupling aware task migration using neighboring core search for many-core systems.Mizunuma, Hitoshi; Lu, Yi-Chang; YI-CHANG LU ; CHIA-LIN YANG 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 201380
502013DuraCache: a durable SSD cache using MLC NAND flash.Liu, Ren-Shuo; Yang, Chia-Lin; Li, Cheng-Hsuan; CHIA-LIN YANG ; CHIA-LIN YANG The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013310
512013Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 201320
522012Guest editorial: Special issue for the 23rd VLSI design/CAD symposium (VLSI design/CAD 2012)Lee, T.-C.; Chien, S.-Y.; Yang, C.-L.; CHIA-LIN YANG International Journal of Electrical Engineering 
532012Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 201260
542012Optimizing NAND flash-based SSDs via retention relaxation.Liu, Ren-Shuo; CHIA-LIN YANG ; Wu, WeiProceedings of the 10th USENIX conference on File and Storage Technologies, FAST 2012, San Jose, CA, USA, February 14-17, 2012105
552012A cycle-level SIMT-GPU simulation framework.Wang, Po-Han; Lo, Chien-Wei; Yang, Chia-Lin; CHIA-LIN YANG ; CHIA-LIN YANG 2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 201270
562012Guest editorial: Special issue for the 23 rd VLSI design/CAD symposium (VLSI design/CAD 2012)Lee, T.-C.; Chien, S.-Y.; Yang, C.-L.; CHIA-LIN YANG International Journal of Electrical Engineering
572012SECRET: Selective error correction for refresh energy reduction in DRAMs.Lin, Chung-Hsiang; Shen, De-Yu; Chen, Yi-Jung; Yang, Chia-Lin; CHIA-LIN YANG ; CHIA-LIN YANG 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012370
582012Age-based PCM wear leveling with nearly zero search cost.Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO ; CHIA-LIN YANG The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012850
592011Thermal modeling and analysis for 3-D ICs with integrated microchannel coolingMizunuma, H.; Lu, Y.-C.; Yang, C.-L.; YI-CHANG LU ; CHIA-LIN YANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4646
602011TACLC: Timing-aware cache leakage control for hard real-time systemsChen, Y.-J.; Yang, C.-L.; Chi, J.-W.; Chen, J.-J.; CHIA-LIN YANG IEEE Transactions on Computers 43
612011Power gating strategies on GPUsWang, P.-H.; Yang, C.-L.; Chen, Y.-M.; Cheng, Y.-J.; CHIA-LIN YANG Transactions on Architecture and Code Optimization 4137
622011A SAT-based routing algorithm for cross-referencing biochips.Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; YAO-WEN CHANG ; CHIA-LIN YANG 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011100
632010Cache-aware task scheduling on multi-core architectureYang, T.-F.; Lin, C.-H.; Yang, C.-L.; CHIA-LIN YANG 2010 International Symposium on VLSI Design, Automation and Test80
642010Memory latency reduction via thread throttlingCheng, H.-Y.; Lin, C.-H.; Li, J.; CHIA-LIN YANG ; CHIA-LIN YANG Annual International Symposium on Microarchitecture370
652010An analytical model to exploit memory task schedulingCheng, H.-Y.; Li, J.; Yang, C.-L.; CHIA-LIN YANG Annual Workshop on Interaction between Compilers and Computer Architectures20
662010Hierarchical memory scheduling for multimedia MPSoCsLin, Y.-J.; Yang, C.-L.; Lin, T.-J.; Huang, J.-W.; CHIA-LIN YANG ; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design90
672010PM-COSYN: PE and memory co-synthesis for MPSoCsChen, Y.-J.; Yang, C.-L.; Wang, P.-H.; CHIA-LIN YANG Design, Automation and Test in Europe
682010PM-COSYN: PE and memory co-synthesis for MPSoCs.Chen, Yi-Jung; Yang, Chia-Lin; Wang, Po-Han; CHIA-LIN YANG Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 201000
692010Parallelization and characterization of GARCH option pricing on GPUs.Liu, Ren-Shuo; Tsai, Yun-Cheng; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings of the 2010 IEEE International Symposium on Workload Characterization, IISWC 2010, Atlanta, GA, USA, December 2-4, 201030
702010Dynamic thermal management for networked embedded systems under harsh ambient temperature variation.Park, Sangyoung; Chen, Jian-Jia; Shin, Donghwa; Kim, Younghyun; Yang, Chia-Lin; CHIA-LIN YANG ; CHIA-LIN YANG Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 201060
712009A Multi-core Architecture Based Parallel Framework for H.264/AVC DeblockingWang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin ; Wu, Ja-LingJournal of Signal Processing Systems 
722009An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip DesignChen, Yi-Jung; Yang, Chia-Lin ; Chang, Yen-ShengJournal of Systems Architecture 1210
732009T-trees: A tree-based representation for temporal and three-dimensional floorplanningYuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems 63
742009PPT: Joint performance/power/thermal management of DRAM memory for multi-core systemsLin, C.-H.; Yang, C.-L.; CHIA-LIN YANG ; CHIA-LIN YANG International Symposium on Low Power Electronics and Design220
752009A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochipsYuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25
762009Thermal modeling for 3D-ICs with integrated microchannel coolingMizunuma, H.; Yang, C.-L.; Lu, Y.-C.; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design
772009Leakage-aware task scheduling for partially dynamically reconfigurable FPGAsYuh, P.-H.; Yang, C.-L.; Li, C.-F.; Lin, C.-H.; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems 73
782009Thermal modeling for 3D-ICs with integrated microchannel cooling.Mizunuma, Hitoshi; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009450
792009A predictive shutdown technique for GPU shader processorsWang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG IEEE Computer Architecture Letters 1612
802009An architectural co-synthesis algorithm for energy-aware network-on-chip design.Hung, Wei-Hsuan; Chen, Yi-Jung; CHIA-LIN YANG ; Chang, Yen-Sheng; CHIA-LIN YANG Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), Seoul, Korea, March 11-15, 200740
812009A multi-core architecture based parallel framework for h.264/avc deblocking filtersWang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU ; CHIA-LIN YANG Journal of Signal Processing Systems 1613
822008兆級晶片系統前瞻技術研究－子計畫一：平台式系統晶片之節能記憶體架構(3/3)楊佳玲 
832008省電與性能最佳化技術:從應用面至系統面之探討－子計畫三：考量能量之網路架構晶片軟硬體共同合成架構　（新制多年期第1年）楊佳玲 
842008兆級晶片系統前瞻技術研究－子計畫一：平台式系統晶片之節能記憶體架構(2/3)楊佳玲 
852008BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochipsYuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7755
862008Obstacle-avoiding rectilinear steiner tree construction based on spanning graphsChen, S.-Y.; Li, C.-F.; CHIA-LIN YANG ; CHUNG-WEI LIN ; YAO-WEN CHANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems5346
872008Energy-aware flash memory management in virtual memory systemLi, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3627
882008Tunablevp: a tunable virtual platform for easy soc design space explorationLin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin; CHIA-LIN YANG 2008 International SoC Design Conference, ISOCC 2008 20
892008A progressive-ILP based routing algorithm for cross-referencing biochipsYuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG Design Automation Conference690
902008A progressive-ILP based routing algorithm for cross-referencing biochips.Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 200800
912007省電與性能最佳化技術:從應用面至系統面之探討－子計畫三：考量能量之網路架構晶片軟硬體共同合成架構　（新制多年期第2年）楊佳玲 
922007Cache Leakage Control Mechanism for Hard Real-Time SystemsChi, Jaw-Wei; CHIA-LIN YANG ; Chen, Yi-Jung; Chen, Jien-Jia2007 international conference on Compilers, architecture, and synthesis for embedded systems 40
932007Temporal floorplanning using the three-dimensional transitive closure subGraphYuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG ACM Transactions on Design Automation of Electronic Systems 2116
942007Post Placement Leakage Optimization for Partially Dynamic Reconfigurable FPGAsLi, Chi-Feng; Yuh, Ping-Hung; Yang, Chia-Lin ; CHIA-LIN YANG International Symposium on Low Power Electronics and Design 70
952007Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic BiochipsYuh, Ping-Hung; Yang, Chia-Lin ; CHIA-LIN YANG IEEE/ACM International Conference on Computer-Aided Design820
962007SoC System Design Program for Computer Science MajorsShih, Chi-Sheng ; Yang, Chia-Lin ; Hung, Shih-Hao ; Hsueh, Chih-Wen ; Chen, Chuen-Liang; Kuo, Tei-Wei 2007 Workshop on Embedded Systems Education 
972007Energy-Efficient Real-Time Task Scheduling with Task RejectionChen, Jian-Jia; Kuo, Tei-Wei ; Yang, Chia-Lin ; King, Ku-JeiDesign, Automation & Test in Europe Conference & Exhibition120
9820073D Video Applications and Intelligent Video Surveillance Camera and its VLSI DesignChien, hao-Yi; Shih, Chi-Sheng ; Ku, Mong-Kai; Yang, Chia-Lin ; Chang, Yao-Wen ; Kuo, Tei-Wei ; Chen, Liang-Gee 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 0
992007Cache Leakage Management for Multi-programming WorkloadsChen, Chun Yang; Yang, Chia Lin ; Hung, Shih Hao Tenth Asia-Pacific Computer Systems Architecture Conference 
10020073D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China00
1012007Efficient obstacle-avoiding rectilinear steiner tree construction.Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG ; CHUNG-WEI LIN Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007360
1022006Branch Behavior Characterization for Multimedia ApplicationsYang, Chia Lin ; Wang, Shun Ying; Chen, Yi JungLecture Notes in Computer Science
1032006Hierarchical Value Cache Encoding for Off-Chip Data BusLin, Chung-Hsiang; Yang, Chia-Lin ; King, Ku-Jei2006 International Symposium on Low Power Electronics and Design
1042006An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary StorageTseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin 2006 International Symposium on Low Power Electronics and Design
1052006Placement of digital microfluidic biochips using the T-tree formuationYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen 43rd annual Design Automation Conference 
1062006A Space-Efficient Caching Mechanism for Flash-Memory Address TranslationWu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin IEEE 9th International Symposium on Object and component-oriented Real-time distributed Computing 90
1072006Branch behavior characterization for multimedia applicationsYang, C.-L.; Wang, S.-Y.; Chen, Y.-J.; CHIA-LIN YANG Lecture Notes in Computer Science
1082006A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.Wu, Chin-Hsien; Kuo, Tei-Wei; CHIA-LIN YANG ; TEI-WEI KUO Ninth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2006), 24-26 April 2006, Gyeongju, Korea00
1092006Hierarchical value cache encoding for off-chip data bus.Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 200630
1102006An energy-efficient virtual memory system with flash memory as the secondary storage.Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006160
1112006Placement of digital microfluidic biochips using the t-tree formulationYuh, P.-H.; Yang, C.-L.; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings - Design Automation Conference440
1122006Branch behavior characterization for multimedia applicationsYang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG Advances in Computer Systems Architecture, Proceedings
1132006Branch Behavior Characterization for Multimedia Applications.Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings00
1142005Software-controlled cache architecture for energy efficiencyYang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU ; Yang, Chia-Lin IEEE Transactions on Circuits and Systems for Video Technology 83
1152005Energy-efficient cache architecture for multimedia applicationsYang, Chia-Lin; Lee, Chien-hao; Tseng, Hung-Wei; CHIA-LIN YANG Emerging Information Technology Conference 2005 00
1162005Phase-Aware I-Cache Size Synthesis with QoS ConsiderationChen, Yi-Jung; Yang, Chia-Lin ; Lin, En-KaiAsia and South Pacific International Conference on Embedded SoCs
1172005先進電子設計自動化技術研發─子計畫一：極大型混合尺寸模組的平面規劃與擺置(2/3)楊佳玲 
1182005Joint exploration of architectural and physical design spaces with thermal considerationWu, Y.-W.; Yang, C.-L.; Yuh, P.-H.; Chang, Y.-W.; CHIA-LIN YANG International Symposium on Low Power Electronics and Design
1192005Reconfigurable platform for content science researchLIANG-GEE CHEN ; TEI-WEI KUO ; YAO-WEN CHANG ; SHAO-YI CHIEN ; CHIA-LIN YANG ; CHI-SHENG SHIH ; Ku, Mong-Kai11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications 00
1202005Joint exploration of architectural and physical design spaces with thermal consideration.Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005180
1212004Temporal floorplanning using the T-tree formulationYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004. 
1222004HotSpot cache: joint temporal and spatial locality exploitation for I-cache energy reductionYang, Chia-Lin ; Lee, Chien-Hao2004 International Symposium on Low Power Electronics and Design00
1232004Multiprocessor energy-efficient scheduling with task migration considerationsChen, Jian-Jia; Hsu, Heng-Ruey; Chuang, Kai-Hsiang; Yang, Chia-Lin ; Pang, Ai-Chun ; Kuo, Tei-Wei 16th Euromicro Conference on Real-Time Systems00
1242004Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive ApplicationsYang, Chia-Lin ; Lebeck, Alvin R.; Tseng, Hung-Wei; Lee, Chien-HaoACM Transactions on Architecture and Code Optimization 17
1252004Energy-efficient flash-memory storage systems with an interrupt-emulation mechanismWu, Chin-Hsien; TEI-WEI KUO ; CHIA-LIN YANG Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 20048
1262004Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.Chen, Jian-Jia; Hsu, Heng-Ruey; Chuang, Kai-Hsiang; Yang, Chia-Lin; Pang, Ai-Chun; AI-CHUN PANG ; CHIA-LIN YANG ; TEI-WEI KUO 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June - 2 July 1004, Catania, Italy, Proceedings00
1272004An Interrupt-Emulation Mechanism with Power-Saving for Flash-Memory Storage SystemsWu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis 
1282004Energy-efficient flash-memory storage systems with an interrupt-emulation mechanismWu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis
1292004Profit-Driven Uniprocessor Scheduling with Energy and Timing ConstraintsChen, Jian-Jia; Kuo, Tei-Wei ; Yang, Chia-Lin 2004 ACM symposium on Applied computing
1302004Temporal Floorplanning Using 3D-subTCGYuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen ; Chen, Hsin-LungAsia and South Pacific Design Automation Conference, ASP-DAC 
1312004Workload characterization of the H.264/AVC decoderShih, T.-T.; Yang, C.-L.; Tung, Y.-S.; CHIA-LIN YANG Lecture Notes in Computer Science
1322004先進電子設計自動化技術研發─子計畫一：極大型混合尺寸模組的平面規劃與擺置(1/3)楊佳玲 
1332004嵌入系統中低功率快取記憶體結構之設計(2/2)楊佳玲 
1342004Value-conscious cache: Simple technique for reducing cache access powerChang, Y.-J.; Yang, C.-L.; CHIA-LIN YANG ; FEI-PEI LAI Design, Automation and Test in Europe20
1352004Temporal floorplanning using the T-tree formulation.Yuh, Ping-Hung; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 200400
1362004Profit-driven uniprocessor scheduling with energy and timing constraints.Chen, Jian-Jia; Kuo, Tei-Wei; CHIA-LIN YANG ; TEI-WEI KUO Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004170
1372004HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.Yang, Chia-Lin; Lee, Chien-Hao; CHIA-LIN YANG Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 200400
1382004Temporal floorplanning using 3D-subTCG.Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 200400
1392004HotSpot Cache: Joint Temporal and Spatial Locality Exploitation for I-Cache Energy ReductionYang, C.-L.; Lee, C.-H.; CHIA-LIN YANG Proceedings of the International Symposium on Low Power Electronics and Design340
1402004Workload Characterization of the H.264/AVC Decoder.Shih, Tse-Tsung; Yang, Chia-Lin; Tung, Yi-Shin; CHIA-LIN YANG Advances in Multimedia Information Processing - PCM 2004, 5th Pacific Rim Conference on Multimedia, Tokyo, Japan, November 30 - December 3, 2004, Proceedings, Part II70
1412003A power-aware SWDR cell for reducing cache write powerChang, Yen-Jen; Yang, Chia-Lin ; Lai, Feipei2003 International Symposium on Low Power Electronics and Design20
1422003Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoderYang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG 2003 Joint Conference of the 4th International Conference on Information, Communications and Signal Processing and 4th Pacific-Rim Conference on Multimedia 20
1432003多媒體通訊系統中可重組化運算技術之研究─子計劃一：可重組化運算之系統分析與設計(I)楊佳玲 
1442003嵌入系統中低功率快取記憶體結構之設計(1/2)楊佳玲 
1452003A power-aware SWDR cell for reducing cache write power.Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei; CHIA-LIN YANG Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 200300
1462002預先擷取鏈結資料結構之可程式化記憶體階層楊佳玲 
1472002Using intel streaming SIMD extensions for 3D geometry processingMa, W.-C.; Yang, C.-L.; CHIA-LIN YANG Lecture Notes in Computer Science
1482002Using Intel Streaming SIMD Extensions for 3D Geometry Processing.Ma, Wan-Chun; Yang, Chia-Lin; CHIA-LIN YANG Advances in Multimedia Information Processing - PCM 2002, Third IEEE Pacific Rim Conference on Multimedia, Hsinchu, Taiwan, December 16-18, 2002, Proceedings70
1492002A programmable memory hierarchy for prefetching linked data structuresYang, C.-L.; Lebeck, A.; CHIA-LIN YANG Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)30
1502002A Programmable Memory Hierarchy for Prefetching Linked Data Structures.Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings30
1512000Push vs. pull: Data movement for linked data structuresYang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG International Conference on Supercomputing 
1522000Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructionsYang, C.-L.; Sano, B.; Lebeck, A.R.; CHIA-LIN YANG IEEE Transactions on Computers 107
1532000Push vs. pull: data movement for linked data structures.Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 200000
1541999Annotated Memory References: A Mechanism for Informed Cache Management.Lebeck, Alvin R.; Raymond, David R.; CHIA-LIN YANG ; Thottethodi, MithunaEuro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings20
1551999Annotated memory references: A mechanism for informed cache managementLebeck, A.R.; Raymond, D.R.; Yang, C.-L.; Thottethodi, M.S.; CHIA-LIN YANG Lecture Notes in Computer Science
1561998Exploiting instruction level parallelism in geometry processing for three dimensional graphics applicationsYang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG Annual International Symposium on Microarchitecture 
1571998Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 199800
158-HotSpot Cache: Saving I-Cache Energy with Dynamic Program Hot Spot Detection for Multimedia ApplicationsYang, Chia-Lin ; Lee, Chien-Hao