Results 1-146 of 146 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12021Opportunities for 2.5/3D Heterogeneous SoC IntegrationJiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; JIUN-LANG HUANG 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings0
22020Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit ModelChen, C.-Y.; Cheng, C.-H.; Huang, J.-L.; Chakrabarty, K.; JIUN-LANG HUANG Proceedings of the European Test Workshop0
32020DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern GeneratorYeh, K.-W.; Huang, J.-L.; JIUN-LANG HUANG Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 20200
42020Intelligent Design Automation for 2.5/3D Heterogeneous SoC IntegrationJiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; JIUN-LANG HUANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD0
52019An FPGA-Based Data Receiver for Digital IC Testing.Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 201900
62019A Multi-Fault Dynamic Compaction Technique for Test Pattern Count ReductionLi, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG Proceedings - International SoC Design Conference 2018, ISOCC 201800
72019Testability Measures Considering Circuit Reconvergence to Reduce ATPG RuntimeChen, K.-H.; Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 201910
82019Reinforcement-Learning-Based Test Program Generation for Software-Based Self-TestChen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG Proceedings of the Asian Test Symposium0
92018Report on 2017 IEEE Asian Test SymposiumLi, Jin-Fu; Huang, Jiun-Lang; JIUN-LANG HUANG Ieee Design & Test00
102018Design and Implementation of an FPGA-Based 16-Channel Data/Timing FormatterHou, G.-H.; Huang, W.-C.; Huang, J.-L.; Kuo, T.; JIUN-LANG HUANG Proceedings of the Asian Test Symposium10
112018Foreword: 26th IEEE Asian test symposium (ATS 2017)Huang, J.-L.; Li, J.-F.; JIUN-LANG HUANG Proceedings of the Asian Test Symposium00
122017Design and implementation of an EG-pool based FPGA formatter with temperature compensationY.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG Asian Test Symposium20
132017Source code transformation for software-based on-line error detectionT.-Y. Tsai; J.-L. Huang; JIUN-LANG HUANG IEEE Conference on Dependable and Secure Computing10
142016An IR-drop guided test pattern generation techniqueL.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG International Symposium on VLSI Design, Automation and Test20
152016A multi-channel FPGA-based time-to-digital converterL.-Y. Hsu; J.-L. Huang; JIUN-LANG HUANG International Mixed-Signal Testing Workshop10
162016CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern GeneratorK.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications01
172016An IR-drop aware test pattern generator for scan-based at-speed testingP.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG Asian Test Symposium10
182015A Test-Application-Count Based Learning Technique for Test Time ReductionG.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
192015Design, automation, and test for low-power and reliable flexible electronicsT.-C. Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG Foundations and Trends in Electronic Design Automation 90
202015A static bidirectional learning technique to accelerate test pattern generationJ.-H. Pan; K.-W. Yeh; J.-L. Huang; JIUN-LANG HUANG International SoC Design Conference00
212015Design and Implementation of an FPGA-Based Data/Timing FormatterY.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications65
222015SDC-TPG: A deterministic zero-inflation parallel test pattern generatorC.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG Asian Test Symposium20
232014逐次逼近暫存器類比數位轉換器及其線性度校正的方法������; ���T��; �L���w; �d���o; JIUN-LANG HUANG 
242014數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器陳弘易; 陳昶聿; 黃炫倫; 黃俊郎; JIUN-LANG HUANG 
252014生成裝置、判別方法、生成方法及びプログラム�d�s�; |���T��; �ž�C; �c�u�T��; JIUN-LANG HUANG 
262014FPGA-Based Subset Sum Delay LinesC.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 20
272013An IDDQ-Based Source Driver IC Design-for-Test TechniqueS.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG International Conference on Computer-Aided Design 00
282013Fault Scrambling Techniques for Yield Enhancement of Embedded MemoriesS.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG Asian Test Symposium 40
292013迴路測試架構與方法JIUN-LANG HUANG ; 黃炫倫; 黃俊郎; 林王安; 康平穎
302013Implementation of programmable delay lines on off-the-shelf FPGAsY.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG IEEE AUTOTESTCON 50
312013A circular pipeline processing based deterministic parallel test pattern generatorK.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG International Test Conference 60
322013測試圖案最佳化的方法JIUN-LANG HUANG ; 吳孟帆; 黃俊郎; 溫曉青; 宮瀨紘平
332013METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAMEHung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG 
342013SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREINXuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG 
352013A mutual characterization based SAR ADC self-testing techniqueH.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG European Test Symposium 40
362013Improve speed path identification with suspect path expressionsJ.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
372013A Low-Cost Error Tolerance Scheme for 3-D CMOS ImagersH.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG IEEE Transactions on Very Large Scale Integration 56
382013On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compressionK. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG International Conference on VLSI Design 50
392013Synergistic reliability and yield enhancement techniques for embedded SRAMsS.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 98
402013ForewordWang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG Proceedings of the Asian Test Symposium00
412012顯示器驅動電路之測試裝置JIUN-LANG HUANG ; 李權哲; 黃俊郎; 黃瑞澤
422012A transition isolation scan cell design for low shift and capture powerY.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG Asian Test Symposium 120
432012Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applicationsY.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 
442012An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and CalibrationX.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications 45
452012A SAR ADC missing-decision level detection and removal techniqueX.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG VLSI Test Symposium 00
462012A fault-tolerant PE array based matrix multiplier designB.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
472012Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG ACM Transactions on Design Automation of Electronic Systems (TODAES) 00
482012Welcome messageWu, C.-W.; Huang, J.-L.; JIUN-LANG HUANG Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 201200
492012Testing and calibration of SAR ADCs by MCT-based bit weight extractionHuang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 201250
502012A built-in characterization technique for 1-bit/stage pipelined ADCChou, Y.-H.; Huang, J.-L.; Huang, X.-L.; JIUN-LANG HUANG Proceedings of the Asian Test Symposium00
512012Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structuresLiu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG Proceedings of SPIE - The International Society for Optical Engineering30
522011Robust Circuit Design for Flexible ElectronicsT.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG IEEE Design & Test of Computers 1110
532011ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and ScalingX.-L. Huang; J.-L. Huang; JIUN-LANG HUANG IEEE Transactions on Very Large Scale Integration 1512
542011Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan TestingY.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG International Test Conference 30
552011A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D ImagerX.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG European Test Symposium 50
562011Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICsW.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG VLSI Test Symposium 10
572011Broadcast test pattern generation considering skew-insertion and partial-serial scanC.-J. Lin; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 30
582011類比數位轉換器���T��; ����A; ���v��; JIUN-LANG HUANG 
592011A self-testing and calibration method for embedded successive approximation register ADCX.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG Asia and South Pacific Design Automation Conference 110
602011Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor depositionHuang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG Proceedings of SPIE - The International Society for Optical Engineering10
612011Guest Editors' Introduction: A Promising Alternative to Conventional SiliconHuang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG Ieee Design & Test of Computers01
622011Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domainsWu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems21
632011On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imagerHuang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 201110
642011Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCsHuang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications (JETTA)32
652011FPAA implementation and validation of an SC integrator leakage measurement techniqueDu, N.-T.; Huang, J.-L.; JIUN-LANG HUANG Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 201100
662011Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first stepChang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 201100
672010Power supply noise reduction in broadcast-based compression environment for at-speed scan testingC.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 40
682010A scalable quantitative measure of IR-drop for scan pattern generationM.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG International Conference on Computer-Aided Design 30
692010An Error Tolerance Scheme for 3D CMOS ImagersH.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG Design Automation Conference 120
702010An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and ScalingXuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG VLSI Test Symposium 80
712010CSER: BISER-based concurrent soft-error resilienceLaung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI ; JIUN-LANG HUANG VLSI Test Symposium (VTS) 20
7220103D-PIC: An Error Tolerant 3D CMOS ImagerH.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG 3D Integration Workshop 
732010A robust ADC code hit counting techniqueJ.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG Design, Automation & Test in Europe 1
742010An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern GenerationM.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG Asia and South Pacific Design Automation Conference 
752010A robust ADC code hit counting technique.Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 201000
762010A robust ADC code hit counting techniqueHuang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG Proceedings -Design, Automation and Test in Europe, DATE1
772010Improved weight assignment for logic switching activity during at-speed test pattern generationWu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC310
782009LPTest: A Flexible Low-Power Test Pattern GeneratorM.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications 75
792009Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression EnvironmentM.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG IEEE Transactions on Compuuter-Aided Design 169
802009An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits TestingC.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 10
812009Analog-to-Digital ConverterJiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG 
822009A Self-Testing Assisted Pipelined-ADC Calibration TechniqueJ.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG International Conference on ASIC 
832009A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC InputX.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG International Journal of Electrical Engineering 
842009A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition MethodK.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG International Conference on Algorithms and Architectures for Parallel Processing 90
852009Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCX.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 10
862009Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC InputX.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG Asia and South Pacific Design Automatic Conference 
872009Ch. 8 Logic and Circuit SimulationJ.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG Electronic Design Automation: Synthesis, Verification, and Test 
882009Logic and Circuit SimulationHuang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG Electronic Design Automation00
892009A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays.Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG JCP00
902009Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC inputHuang, X.-L.; Yang, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC20
912008A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line StabilizationP.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG International Symposium on Flexible Electronics and Displays 
922008PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression EnvironmentY.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 40
932008Testing LCD Source Driver IC with Built-On-Scribe-Line Test CircuitryJ.-J. Huang; J.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 20
942008Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed TestingM.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG International Test Conference 460
952008可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(2/3)黃俊郎 
962008多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(1/3)黃俊郎 
972008可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(1/3)黃俊郎 
982008Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCsX.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG International Mixed-Signals, Sensors, and Systems Test Workshop 60
992008A Self-Testing and Calibration Technique for Current-Steering DACsY.-L. Ma; J.-L. Huang; JIUN-LANG HUANG International Symposium on VLSI Design, Automation, and Test 00
1002008Design of a Fault Tolerant Carry Lookahead AdderC.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG International Test Synthesis Workshop 
1012008A Built-In TFT Array Charge-Sensing Technique for System-on-Panel DisplaysC.-W. Lin; Jiun-Lang Huang; JIUN-LANG HUANG VLSI Test Symposium 110
1022008Software-Based Self-TestingHuang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG System-on-Chip Test Architectures00
1032008On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designsWu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Apte, R.; JIUN-LANG HUANG Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems00
1042007An Efficient Peak Power Reduction Technique for Scan TestingM.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 180
1052007A Low Cost Spectral Power Extraction Technique for RF Transceiver TestingT.-L. Hung; J.-L. Huang; JIUN-LANG HUANG VLSI Test Symposium 20
1062007Chap. 11 Software-Based Self-TestingJ.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG System on Chip Test Architectures 
1072006On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay LinesJ.-L. Huang; JIUN-LANG HUANG Journal of Electronic Testing: Theory and Applications 21
1082006A Random Jitter Extraction Technique in the Presence of Sinusoidal JitterJ.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 30
1092006An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance TestingS.-W. Chang; J.-L. Huang; JIUN-LANG HUANG VLSI Design/CAD Symposium 
1102006Chap. 3: Logic and Fault SimulationJ.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG VLSI Test Principles and Architectures 
1112006Extracting Random Jitter in the Existence of Sinusoidal JitterJ.-L. Huang; JIUN-LANG HUANG International Mixed-Signal Testing Workshop 
1122006A low-cost jitter measurement technique for BIST applicationsJ.-L. Huang; J.-J. Huang; Y.-S. Liu; Huang, Jiun-Lang Journal of Electronic Testing: Theory and Appications 64
1132006A period tracking based on-chip sinusoidal jitter extraction techniqueC.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG VLSI Test Symposium 60
1142006A routability constrained scan chain ordering technique for test power reductionX.-L. Huang; J.-L. Huang; JIUN-LANG HUANG Asia and South Pacific Design Automation Conference 7
1152006Logic and fault simulationHuang, J.-L.; Li, J.C.-M.; Walker, D.M.; JIUN-LANG HUANG VLSI Test Principles and Architectures00
1162005Random jitter testing using low tap-count delay linesJ.-L. Huang; JIUN-LANG HUANG Asian Test Symposium 00
1172005子計畫三:高速資料傳輸系統的可測試性設計技術(2/3)黃俊郎 
1182005類比前端電路的內建自我測試技術黃俊郎 
1192005An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay LinesJ. L. Huang; JIUN-LANG HUANG International Mixed-Signal Testing Workshop 
1202005A Fabrication Process Variation Based Approach to Evaluate Design-for-Test TechniquesY. R. Chen; J. L. Huang; JIUN-LANG HUANG Bulletin of the College of Engineering
1212005製程偏移對可測試性設計技術效能影響的評估陳逸任; 黃俊郎 ; Chen, Yi-Ren; Huang, Jiun-Lang Bulletin of the College of Engineering 
1222004An Infrastructure IP for On-Chip Clock Jitter MeasurementJ. J. Huang; J. L. Huang; JIUN-LANG HUANG International Conference on Conmputer Design 2
1232004子計畫三:高速資料傳輸系統的可測試性設計技術(1/3)黃俊郎 
1242004子計畫四:類比前端電路的內建自我測試技術黃俊郎 
1252004An Infrastructure IP for On-Chip Clock Jitter Measurement.Huang, Jui-Jer; Huang, Jiun-Lang; JIUN-LANG HUANG 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings00
1262003高速串列通信傳送媒介之測試黃俊郎 
1272003A Low-Cost Jitter Measurement Technique for BIST ApplicationsJ. J. Huang; J. L. Huang; JIUN-LANG HUANG Asian Test Symposium 144
1282003Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data SystemsH. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG IEEE Transactions on Circuits and Systems II 2924
1292003A Delay-Line Based On-Chip Jitter Measurement TechniqueJ. J. Huang; J. L. Huang; JIUN-LANG HUANG VLSI Design/CAD Symposium 
1302003子計劃六:可重組化運算之測試設計(I)黃俊郎 
1312003Practical Considerations in Applying-Modulation-Based Analog BIST to Sampled-Data SystemsHong, Hao-Chiao; Huang, Jiun-Lang ; Cheng, Kwang-Ting; Wu, Cheng-Wen; Kwai, Ding-MingIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 
1322002On-Chip Analog Response Extraction with 1-Bit Sigma-Delta ModulatorsH. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG Asian Test Symposium 110
1332002Testing Second-Order Delta-Sigma Modulators using Pseudo-Random PatternsC. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG Microelectronics Journal 63
1342002A BIST Scheme for the Embedded ADC in ADSL SoCY. J. Chang; S. J. Chang; C. K. Ong; J. C. Ho; J. L. Huang; K. T. Cheng; W. C. Wu; JIUN-LANG HUANG VLSI Design/CAD Symposium 
1352001An on-chip short-time interval measurement technique for testing high-speed communication linksJ.L. Huang; K.T. Cheng; JIUN-LANG HUANG VLSI Test Symposium 21
1362001An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links.Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA00
1372000Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.Tofte, Jan Arild; Ong, Chee-Kian; Huang, Jiun-Lang; Cheng, Kwang-Ting (Tim); JIUN-LANG HUANG 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada00
1382000A delta-sigma modulation based BIST scheme for mixed-signal systemsHuang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 200010
1392000A sigma-delta modulation based BIST scheme for mixed-signal circuitsHuang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC250
1402000Test point selection for analog fault diagnosis of unpowered circuit boardsHuang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing1716
1412000A BIST scheme for on-chip ADC and DAC testingHuang, J.-L.; Ong, C.-K.; Cheng, K.-T.; JIUN-LANG HUANG Proceedings -Design, Automation and Test in Europe, DATE1310
1422000Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-testTofte, Jan Arild, Ong, Chee-Kian, Huang, Jiun-Lang, Cheng, Kwang-Ting; JIUN-LANG HUANG Proceedings of the IEEE VLSI Test Symposium13
1432000Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis.Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 200000
1441999Specification back-propagation and its application to fault simulation of analog/mixed-signal circuitsJ. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG VLSI Test Symposium 12
1451999Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits.Huang, Jiun-Lang; Pan, Chen-Yang; Cheng, Kwang-Ting; JIUN-LANG HUANG 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA00
1461997Analog fault diagnosis for unpowered circuit boardsHuang, Jiun-Lang, Cheng, Kwang-Ting; JIUN-LANG HUANG IEEE International Test Conference (TC)30