第 1 到 25 筆結果,共 25 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2019 | Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test | Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 9 | 0 | |
2 | 2019 | A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction | Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - International SoC Design Conference 2018, ISOCC 2018 | 0 | 0 | |
3 | 2018 | Foreword: 26th IEEE Asian test symposium (ATS 2017) | Huang, J.-L.; Li, J.-F.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
4 | 2018 | Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter | Hou, G.-H.; Huang, W.-C.; Huang, J.-L.; Kuo, T.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 1 | 0 | |
5 | 2013 | Foreword | Wang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
6 | 2012 | Testing and calibration of SAR ADCs by MCT-based bit weight extraction | Huang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 7 | 0 | |
7 | 2012 | Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures | Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 4 | 0 | |
8 | 2012 | Welcome message | Wu, C.-W.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 0 | 0 | |
9 | 2012 | A built-in characterization technique for 1-bit/stage pipelined ADC | Chou, Y.-H.; Huang, J.-L.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
10 | 2011 | On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager | Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
11 | 2011 | Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step | Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
12 | 2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
13 | 2011 | Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition | Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 1 | 0 | |
14 | 2011 | FPAA implementation and validation of an SC integrator leakage measurement technique | Du, N.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
15 | 2011 | Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs | Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 3 | 2 | |
16 | 2010 | A robust ADC code hit counting technique | Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | 1 | ||
17 | 2010 | Improved weight assignment for logic switching activity during at-speed test pattern generation | Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 33 | 0 | |
18 | 2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG | Electronic Design Automation | 2 | 0 | |
19 | 2009 | Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input | Huang, X.-L.; Yang, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
20 | 2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
21 | 2008 | Software-Based Self-Testing | Huang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG | System-on-Chip Test Architectures | 0 | 0 | |
22 | 2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
23 | 2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 18 | 16 | |
24 | 2000 | A delta-sigma modulation based BIST scheme for mixed-signal systems | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000 | 1 | 0 | |
25 | 2000 | A BIST scheme for on-chip ADC and DAC testing | Huang, J.-L.; Ong, C.-K.; Cheng, K.-T.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | 136 | 0 |