第 1 到 9 筆結果,共 9 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | CHIEN-MO LI ; JIUN-LANG HUANG ; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | ||
2 | 2005 | A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques | Y. R. Chen; J. L. Huang; JIUN-LANG HUANG | Bulletin of the College of Engineering | |||
3 | 2004 | An Infrastructure IP for On-Chip Clock Jitter Measurement | J. J. Huang; J. L. Huang; JIUN-LANG HUANG | International Conference on Conmputer Design | 9 | ||
4 | 2003 | Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II | 29 | 24 | |
5 | 2003 | A Delay-Line Based On-Chip Jitter Measurement Technique | J. J. Huang; J. L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
6 | 2002 | On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG | Asian Test Symposium | 11 | 0 | |
7 | 2002 | Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns | C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG | Microelectronics Journal | 6 | 3 | |
8 | 2002 | A BIST Scheme for the Embedded ADC in ADSL SoC | Y. J. Chang; S. J. Chang; C. K. Ong; J. C. Ho; J. L. Huang; K. T. Cheng; W. C. Wu; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
9 | 1999 | Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits | J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG | VLSI Test Symposium | 12 |