第 1 到 145 筆結果,共 145 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2022 | Test Response Compaction for Software-Based Self-Test | Liang, Jia Ruei; Hsieh, Ya Ni; JIUN-LANG HUANG | Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 | 0 | 0 | |
2 | 2022 | Welcome Message ITC-Asia 2022 | Chang, Soon Jyh; JIUN-LANG HUANG | Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022 | 0 | 0 | |
3 | 2021 | Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors | Chen, Kai Hsun; Yang, Bo Yi; Liang, Jia Ruei; Chen, Hung Lin; JIUN-LANG HUANG | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 2 | 0 | |
4 | 2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
5 | 2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
6 | 2020 | Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model | Chen, C.-Y.; Cheng, C.-H.; JIUN-LANG HUANG ; Chakrabarty, K. | Proceedings of the European Test Workshop | 3 | 0 | |
7 | 2020 | DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator | Yeh, K.-W.; JIUN-LANG HUANG | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | 0 | 0 | |
8 | 2019 | An FPGA-Based Data Receiver for Digital IC Testing. | Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG | IEEE International Test Conference in Asia, ITC-Asia 2019, Tokyo, Japan, September 3-5, 2019 | 3 | 0 | |
9 | 2019 | Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test | Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 9 | 0 | |
10 | 2019 | A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction | Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - International SoC Design Conference 2018, ISOCC 2018 | 0 | 0 | |
11 | 2019 | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime | Chen, K.-H.; Chen, C.-Y.; JIUN-LANG HUANG | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 | 3 | 0 | |
12 | 2018 | Foreword: 26th IEEE Asian test symposium (ATS 2017) | Huang, J.-L.; Li, J.-F.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
13 | 2018 | Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter | Hou, G.-H.; Huang, W.-C.; Huang, J.-L.; Kuo, T.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 1 | 0 | |
14 | 2018 | Conference Reports: Report on 2017 IEEE Asian Test Symposium | Li, Jin-Fu; JIUN-LANG HUANG | IEEE Design and Test | 0 | 0 | |
15 | 2017 | Source code transformation for software-based on-line error detection | T.-Y. Tsai; J.-L. Huang; JIUN-LANG HUANG | IEEE Conference on Dependable and Secure Computing | 3 | 0 | |
16 | 2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
17 | 2016 | A multi-channel FPGA-based time-to-digital converter | L.-Y. Hsu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | 1 | 0 | |
18 | 2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
19 | 2016 | An IR-drop guided test pattern generation technique | L.-C. Tsai; J.-Z. Li; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation and Test | 4 | 0 | |
20 | 2016 | An IR-drop aware test pattern generator for scan-based at-speed testing | P.-F. Hou; Y.-T. Lin; J.-L. Huang; A. Shih; Z. F. Conroy; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
21 | 2015 | Design, automation, and test for low-power and reliable flexible electronics | T.-C. Huang; JIUN-LANG HUANG ; K.-T. Cheng | Foundations and Trends in Electronic Design Automation | 10 | 0 | |
22 | 2015 | A Test-Application-Count Based Learning Technique for Test Time Reduction | G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
23 | 2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
24 | 2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
25 | 2015 | A static bidirectional learning technique to accelerate test pattern generation | J.-H. Pan; K.-W. Yeh; J.-L. Huang; JIUN-LANG HUANG | International SoC Design Conference | 0 | 0 | |
26 | 2014 | 逐次逼近暫存器類比數位轉換器及其線性度校正的方法 | ������; ���T��; �L���w; �d���o; JIUN-LANG HUANG | ||||
27 | 2014 | 數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器 | 陳弘易; 陳昶聿; 黃炫倫; 黃俊郎; JIUN-LANG HUANG | ||||
28 | 2014 | 生成裝置、判別方法、生成方法及びプログラム | 吳孟帆; 黃俊郎 ; 溫曉青; 宮瀨紘平 | ||||
29 | 2014 | FPGA-Based Subset Sum Delay Lines | C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
30 | 2013 | An IDDQ-Based Source Driver IC Design-for-Test Technique | S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 0 | 0 | |
31 | 2013 | Fault Scrambling Techniques for Yield Enhancement of Embedded Memories | S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG | Asian Test Symposium | 5 | 0 | |
32 | 2013 | A circular pipeline processing based deterministic parallel test pattern generator | K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG | International Test Conference | 9 | 0 | |
33 | 2013 | 迴路測試架構與方法 | JIUN-LANG HUANG ; 黃炫倫; 黃俊郎; 林王安; 康平穎 | ||||
34 | 2013 | Implementation of programmable delay lines on off-the-shelf FPGAs | Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | IEEE AUTOTESTCON | 8 | 0 | |
35 | 2013 | METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME | Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | ||||
36 | 2013 | 測試圖案最佳化的方法 | JIUN-LANG HUANG ; 吳孟帆; 黃俊郎; 溫曉青; 宮瀨紘平 | ||||
37 | 2013 | SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN | Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | ||||
38 | 2013 | A mutual characterization based SAR ADC self-testing technique | H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
39 | 2013 | Improve speed path identification with suspect path expressions | J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
40 | 2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
41 | 2013 | Synergistic reliability and yield enhancement techniques for embedded SRAMs | S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 8 | |
42 | 2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
43 | 2013 | Foreword | Wang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
44 | 2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | |||
45 | 2012 | A transition isolation scan cell design for low shift and capture power | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | Asian Test Symposium | 13 | 0 | |
46 | 2012 | 顯示器驅動電路之測試裝置 | JIUN-LANG HUANG ; 李權哲; 黃俊郎; 黃瑞澤 | ||||
47 | 2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 | |
48 | 2012 | A fault-tolerant PE array based matrix multiplier design | B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 0 | 0 | |
49 | 2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
50 | 2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | 0 | |
51 | 2012 | Testing and calibration of SAR ADCs by MCT-based bit weight extraction | Huang, X.-L.; Chen, H.-I.; Huang, J.-L.; Chen, C.-Y.; Kuo-Tsai, T.; Huang, M.-F.; Chou, Y.-F.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 7 | 0 | |
52 | 2012 | Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures | Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P.; Huang, J.-J.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 4 | 0 | |
53 | 2012 | Welcome message | Wu, C.-W.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012 | 0 | 0 | |
54 | 2012 | A built-in characterization technique for 1-bit/stage pipelined ADC | Chou, Y.-H.; Huang, J.-L.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 0 | 0 | |
55 | 2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
56 | 2011 | ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 16 | 14 | |
57 | 2011 | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | International Test Conference | 3 | 0 | |
58 | 2011 | A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager | X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
59 | 2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs | W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 1 | 0 | |
60 | 2011 | Broadcast test pattern generation considering skew-insertion and partial-serial scan | C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
61 | 2011 | A self-testing and calibration method for embedded successive approximation register ADC | X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 11 | 0 | |
62 | 2011 | On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager | Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 1 | 0 | |
63 | 2011 | Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step | Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
64 | 2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
65 | 2011 | Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition | Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG | Proceedings of SPIE - The International Society for Optical Engineering | 1 | 0 | |
66 | 2011 | Guest Editors' Introduction: A Promising Alternative to Conventional Silicon | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Ieee Design & Test of Computers | 0 | 1 | |
67 | 2011 | FPAA implementation and validation of an SC integrator leakage measurement technique | Du, N.-T.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | 0 | 0 | |
68 | 2011 | Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs | Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 3 | 2 | |
69 | 2010 | Power supply noise reduction in broadcast-based compression environment for at-speed scan testing | C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
70 | 2010 | A scalable quantitative measure of IR-drop for scan pattern generation | M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 4 | 0 | |
71 | 2010 | An Error Tolerance Scheme for 3D CMOS Imagers | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | Design Automation Conference | 13 | 0 | |
72 | 2010 | CSER: BISER-based concurrent soft-error resilience | Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | 2 | 0 | |
73 | 2010 | An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling | Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | VLSI Test Symposium | 9 | 0 | |
74 | 2010 | A robust ADC code hit counting technique | J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG | Design, Automation & Test in Europe | 1 | ||
75 | 2010 | 3D-PIC: An Error Tolerant 3D CMOS Imager | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | 3D Integration Workshop | |||
76 | 2010 | An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation | M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | |||
77 | 2010 | A robust ADC code hit counting technique | Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | 1 | ||
78 | 2010 | Improved weight assignment for logic switching activity during at-speed test pattern generation | Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 33 | 0 | |
79 | 2010 | A robust ADC code hit counting technique. | Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG | Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010 | 0 | 0 | |
80 | 2009 | LPTest: A Flexible Low-Power Test Pattern Generator | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 7 | 5 | |
81 | 2009 | Analog-to-Digital Converter | Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG | ||||
82 | 2009 | An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing | C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 1 | 0 | |
83 | 2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
84 | 2009 | A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input | X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG | International Journal of Electrical Engineering | |||
85 | 2009 | A Self-Testing Assisted Pipelined-ADC Calibration Technique | J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG | International Conference on ASIC | |||
86 | 2009 | A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method | K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | International Conference on Algorithms and Architectures for Parallel Processing | 10 | 0 | |
87 | 2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
88 | 2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | |||
89 | 2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | |||
90 | 2009 | Logic and Circuit Simulation | Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG | Electronic Design Automation | 2 | 0 | |
91 | 2009 | Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input | Huang, X.-L.; Yang, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
92 | 2009 | A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. | Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG | JCP | 0 | 0 | |
93 | 2008 | Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry | J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
94 | 2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
95 | 2008 | A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization | P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG | International Symposium on Flexible Electronics and Displays | |||
96 | 2008 | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | International Test Conference | 48 | 0 | |
97 | 2008 | 多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(1/3) | 黃俊郎 | ||||
98 | 2008 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(2/3) | 黃俊郎 | ||||
99 | 2008 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(1/3) | 黃俊郎 | ||||
100 | 2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
101 | 2008 | A Self-Testing and Calibration Technique for Current-Steering DACs | Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 4 | 0 | |
102 | 2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | |||
103 | 2008 | A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays | C.-W. Lin; Jiun-Lang Huang; JIUN-LANG HUANG | VLSI Test Symposium | 11 | 0 | |
104 | 2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
105 | 2008 | Software-Based Self-Testing | Huang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG | System-on-Chip Test Architectures | 0 | 0 | |
106 | 2007 | An Efficient Peak Power Reduction Technique for Scan Testing | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 18 | 0 | |
107 | 2007 | A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing | T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 2 | 0 | |
108 | 2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | |||
109 | 2006 | On-chip random jitter testing using low tap-count coarse delay lines | JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 2 | 1 | |
110 | 2006 | A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter | J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 6 | 0 | |
111 | 2006 | An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing | S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
112 | 2006 | A low-cost jitter measurement technique for BIST applications | JIUN-LANG HUANG ; J.-J. Huang; Y.-S. Liu | Journal of Electronic Testing: Theory and Applications (JETTA) | 6 | 4 | |
113 | 2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | |||
114 | 2006 | Extracting Random Jitter in the Existence of Sinusoidal Jitter | J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | |||
115 | 2006 | A period tracking based on-chip sinusoidal jitter extraction technique | C.-Y. Kuo; JIUN-LANG HUANG | Proceedings of the IEEE VLSI Test Symposium | 8 | 0 | |
116 | 2006 | A routability constrained scan chain ordering technique for test power reduction | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 8 | ||
117 | 2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
118 | 2005 | Random jitter testing using low tap-count delay lines | J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 0 | 0 | |
119 | 2005 | 類比前端電路的內建自我測試技術 | 黃俊郎 | ||||
120 | 2005 | 子計畫三:高速資料傳輸系統的可測試性設計技術(2/3) | 黃俊郎 | ||||
121 | 2005 | An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines | J. L. Huang; JIUN-LANG HUANG | International Mixed-Signal Testing Workshop | |||
122 | 2005 | 製程偏移對可測試性設計技術效能影響的評估 | 陳逸任; 黃俊郎 ; Chen, Yi-Ren; Huang, Jiun-Lang | Bulletin of the College of Engineering | |||
123 | 2005 | A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques | Y. R. Chen; J. L. Huang; JIUN-LANG HUANG | Bulletin of the College of Engineering | |||
124 | 2004 | An Infrastructure IP for On-Chip Clock Jitter Measurement | J. J. Huang; J. L. Huang; JIUN-LANG HUANG | International Conference on Conmputer Design | 9 | ||
125 | 2004 | 子計畫四:類比前端電路的內建自我測試技術 | 黃俊郎 | ||||
126 | 2004 | 子計畫三:高速資料傳輸系統的可測試性設計技術(1/3) | 黃俊郎 | ||||
127 | 2004 | An Infrastructure IP for On-Chip Clock Jitter Measurement. | Huang, Jui-Jer; Huang, Jiun-Lang; JIUN-LANG HUANG | 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings | 0 | 0 | |
128 | 2003 | 高速串列通信傳送媒介之測試 | 黃俊郎 | ||||
129 | 2003 | A low-cost jitter measurement technique for BIST applications | J. J. Huang; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | 18 | 4 | |
130 | 2003 | Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II | 29 | 24 | |
131 | 2003 | A Delay-Line Based On-Chip Jitter Measurement Technique | J. J. Huang; J. L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
132 | 2003 | 子計劃六:可重組化運算之測試設計(I) | 黃俊郎 | ||||
133 | 2003 | Practical Considerations in Applying-Modulation-Based Analog BIST to Sampled-Data Systems | Hong, Hao-Chiao; Huang, Jiun-Lang ; Cheng, Kwang-Ting; Wu, Cheng-Wen; Kwai, Ding-Ming | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | |||
134 | 2002 | On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG | Asian Test Symposium | 11 | 0 | |
135 | 2002 | Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns | C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG | Microelectronics Journal | 6 | 3 | |
136 | 2002 | A BIST Scheme for the Embedded ADC in ADSL SoC | Y. J. Chang; S. J. Chang; C. K. Ong; J. C. Ho; J. L. Huang; K. T. Cheng; W. C. Wu; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
137 | 2001 | An on-chip short-time interval measurement technique for testing high-speed communication links | J.L. Huang; K.T. Cheng; JIUN-LANG HUANG | VLSI Test Symposium | 24 | ||
138 | 2001 | An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA | 0 | 0 | |
139 | 2000 | Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. | Tofte, Jan Arild; Ong, Chee-Kian; Huang, Jiun-Lang; Cheng, Kwang-Ting (Tim); JIUN-LANG HUANG | 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada | 0 | 0 | |
140 | 2000 | A sigma-delta modulation based BIST scheme for mixed-signal circuits | JIUN-LANG HUANG ; Cheng, K.-T. | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 27 | 0 | |
141 | 2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 18 | 16 | |
142 | 2000 | Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | 0 | 0 | |
143 | 2000 | A delta-sigma modulation based BIST scheme for mixed-signal systems | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000 | 1 | 0 | |
144 | 2000 | Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test | Tofte, Jan Arild, Ong, Chee-Kian, Huang, Jiun-Lang, Cheng, Kwang-Ting; JIUN-LANG HUANG | Proceedings of the IEEE VLSI Test Symposium | 14 | ||
145 | 2000 | A BIST scheme for on-chip ADC and DAC testing | Huang, J.-L.; Ong, C.-K.; Cheng, K.-T.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | 136 | 0 |