第 1 到 27 筆結果,共 27 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2009 | A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input | X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG | International Journal of Electrical Engineering | |||
2 | 2005 | A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques | Y. R. Chen; J. L. Huang; JIUN-LANG HUANG | Bulletin of the College of Engineering | |||
3 | 2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
4 | 2011 | ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 16 | 14 | |
5 | 2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 | |
6 | 2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | |||
7 | 2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | |||
8 | 2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | |||
9 | 2000 | Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test | Tofte, Jan Arild, Ong, Chee-Kian, Huang, Jiun-Lang, Cheng, Kwang-Ting; JIUN-LANG HUANG | Proceedings of the IEEE VLSI Test Symposium | 14 | ||
10 | 2009 | A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. | Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG | JCP | 0 | 0 | |
11 | 2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
12 | 2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
13 | 2015 | Design, automation, and test for low-power and reliable flexible electronics | T.-C. Huang; JIUN-LANG HUANG ; K.-T. Cheng | Foundations and Trends in Electronic Design Automation | 10 | 0 | |
14 | 2011 | Guest Editors' Introduction: A Promising Alternative to Conventional Silicon | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | Ieee Design & Test of Computers | 0 | 1 | |
15 | 2011 | Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs | Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 3 | 2 | |
16 | 2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | 0 | |
17 | 2009 | LPTest: A Flexible Low-Power Test Pattern Generator | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 7 | 5 | |
18 | 2006 | On-chip random jitter testing using low tap-count coarse delay lines | JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 2 | 1 | |
19 | 2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
20 | 2003 | Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II | 29 | 24 | |
21 | 2003 | Practical Considerations in Applying-Modulation-Based Analog BIST to Sampled-Data Systems | Hong, Hao-Chiao; Huang, Jiun-Lang ; Cheng, Kwang-Ting; Wu, Cheng-Wen; Kwai, Ding-Ming | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | |||
22 | 2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
23 | 2013 | Synergistic reliability and yield enhancement techniques for embedded SRAMs | S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 8 | |
24 | 2000 | Test point selection for analog fault diagnosis of unpowered circuit boards | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 18 | 16 | |
25 | 2002 | Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns | C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG | Microelectronics Journal | 6 | 3 | |
26 | 2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
27 | 2005 | 製程偏移對可測試性設計技術效能影響的評估 | 陳逸任; 黃俊郎 ; Chen, Yi-Ren; Huang, Jiun-Lang | Bulletin of the College of Engineering |