Projects
(Principal Investigator)



Results 1-36 of 36 (Search time: 0.006 seconds).

Start DateTitleP-InvestigatorFunding Organization/經費來源
2020以軟體為基礎的處理器核心自我測試技術之研發JIUN-LANG HUANGMinistry of Science and Technology
2019提升CPU核心使用期間可靠度的軟體自我測試技術之研發JIUN-LANG HUANGMinistry of Science and Technology
2018下世代前瞻電子設計自動化技術-子計畫五:針對下世代製程發展具決定性之平行化測試圖樣產生技術JIUN-LANG HUANGMinistry of Science and Technology
2017下世代前瞻電子設計自動化技術-子計畫五:針對下世代製程發展具決定性之平行化測試圖樣產生技術JIUN-LANG HUANGMinistry of Science and Technology
2016下世代前瞻電子設計自動化技術-子計畫五:針對下世代製程發展具決定性之平行化測試圖樣產生技術JIUN-LANG HUANGMinistry of Science and Technology
2015以平行化搜尋技術降低測試圖樣數目的決定性自動測試圖樣產生技術之研發JIUN-LANG HUANGMinistry of Science and Technology
2014考慮次10奈米製程晶片複雜度與變異性的平行化測試圖樣產生與適性測試技術之開發(I)JIUN-LANG HUANGMinistry of Science and Technology
2014實現奈米級超大型CMOS積體電路之前瞻測試技術JIUN-LANG HUANGMinistry of Science and Technology
2013氣喘環境因子之多重感測網路及雲端系統-子計畫三:氣喘環境因子感測器測試與校正技術JIUN-LANG HUANGMinistry of Science and Technology
2013實現奈米級超大型CMOS積體電路之前瞻測試技術JIUN-LANG HUANGMinistry of Science and Technology
2012智慧型非侵入陣列式血流監控系統晶片-子計畫四:類比前端陣列內建自我測試與校正技術之研發(3/3)JIUN-LANG HUANGMinistry of Science and Technology
2012科學工業園區研發精進產學合作計畫—平行化測試圖樣產生器之研發與實現JIUN-LANG HUANGHsinchu Science Park Bureau, MOST
2012實現奈米級超大型CMOS積體電路之前瞻測試技術JIUN-LANG HUANGMinistry of Science and Technology
2011智慧型非侵入陣列式血流監控系統晶片-子計畫四:類比前端陣列內建自我測試與校正技術之研發(2/3)JIUN-LANG HUANGMinistry of Science and Technology
2010科學工業園區研發精進產學合作計畫—分散式自動設計圖樣產生器之研發JIUN-LANG HUANGHsinchu Science Park Bureau, MOST
2010智慧型非侵入陣列式血流監控系統晶片-子計畫四:類比前端陣列內建自我測試與校正技術之研發(1/3)JIUN-LANG HUANGMinistry of Science and Technology
200998學年大學校院積體電路電腦輔助設計(CAD)軟體製作競賽JIUN-LANG HUANGMinistry of Education
2009在測試壓縮環境下的低電壓下降全速測試圖樣產生技術之研發JIUN-LANG HUANGMinistry of Science and Technology
2009多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(3/3)JIUN-LANG HUANGMinistry of Science and Technology
2009跨國產學合作計畫-美國 Mentor Graphics Corporation 短期研習JIUN-LANG HUANGMinistry of Science and Technology
2008可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(3/3)JIUN-LANG HUANGMinistry of Science and Technology
2008多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(2/3)JIUN-LANG HUANGMinistry of Science and Technology
2008大學校院積體電路電腦輔助設計(CAD)軟體製作競賽JIUN-LANG HUANGAdvisory Office, MOE
2008大學校院積體電路電腦輔助設計(CAD)軟體製作競賽JIUN-LANG HUANGAdvisory Office, MOE
2007可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(2/3)JIUN-LANG HUANGMinistry of Science and Technology
2007多媒體系統無線傳輸介面之研發-子計畫五:以內建自我測試為基礎的ADC/DAC校正與修復技術之研發(1/3)JIUN-LANG HUANGMinistry of Science and Technology
2006可應用於軟性電子的TFT電路設計技術之開發-子計畫五:適用於軟性顯示器TFT陣列的缺陷容忍技術之開發(1/3)JIUN-LANG HUANGMinistry of Science and Technology
2005高效能類比積體電路之研製-子計畫三:高速資料傳輸系統的可測試性設計技術(3/3)JIUN-LANG HUANGMinistry of Science and Technology
2005具有內建自我測試功能之5GHz超低功率無線通訊系統之研製-子計畫四:類比前端電路的內建自我測試技術(2/2)JIUN-LANG HUANGMinistry of Science and Technology
2004具有內建自我測試功能之5GHz超低功率無線通訊系統之研製-子計畫四:類比前端電路的內建自我測試技術(1/2)JIUN-LANG HUANGMinistry of Science and Technology
2004高效能類比積體電路之研製-子計畫三:高速資料傳輸系統的可測試性設計技術(2/3)JIUN-LANG HUANGMinistry of Science and Technology
2003高效能類比積體電路之研製-子計畫三:高速資料傳輸系統的可測試性設計技術(1/3)JIUN-LANG HUANGMinistry of Science and Technology
2003具有內建自我測試功能之5GHz超低功率無線通訊系統之研製-子計畫四:類比前端電路的內建自我測試技術JIUN-LANG HUANGMinistry of Science and Technology
2002提昇產業技術及人才培育研究計劃--高速串列通信傳送媒介之測試JIUN-LANG HUANGMinistry of Science and Technology
2002高速串列通信傳送媒介之測試JIUN-LANG HUANGMinistry of Science and Technology
2002多媒體通訊系統中可重組化運算技術之研究-子計畫六:可重組化運算之測試設計(Ⅰ)JIUN-LANG HUANGMinistry of Science and Technology