Results 1-146 of 146 (Search time: 0.009 seconds).

Issue DateTitleAuthor(s)TypescopusWOSFulltext/Archive link
12019ATPG and test compression for probabilistic circuitsYang, K.-C.; Lee, M.-T.; Wu, C.-H.; Li, J.C.-M.; CHIEN-MO LI conference paper00
22019Test methodology for PCHB/PCFB Asynchronous CircuitsShen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; Pan, S.; CHIEN-MO LI conference paper00
32018DR-scan: Dual-rail Asynchronous Scan DfT and ATPGShih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai Tsai-Chieh Chen; James Chien-Mo Li; CHIEN-MO LI journal article00
42018Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree constructionWang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W.; Li, J.C.M.; Jiang, J.-H.R.; CHIEN-MO LI conference paper30
52018Machine-learning-based dynamic IR drop prediction for ECOFang, Y.-C.; Lin, H.-Y.; Su, M.-Y.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI conference paper50
62018Test methodology for PCHB/PCFB Asynchronous Circuits.Shen, Ting-Yu; Pai, Chia-Cheng; Chen, Tsai-Chieh; Li, James Chien-Mo; Pan, Samuel; CHIEN-MO LI conference paper00
72018Parallel order ATPG for test compactionChen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI conference paper00
82018Diagnosis and repair of cells (DRC) responsible for power-supply-noise violationsLi, Y.-C.; Lin, S.-Y.; Lin, H.-Y.; Li, J.C.-M.; CHIEN-MO LI conference paper00
92018IR drop prediction of ECO-revised circuits using machine learningLin, S.-Y.; Fang, Y.-C.; Li, Y.-C.; Liu, Y.-C.; Yang, T.-S.; Lin, S.-C.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI conference paper60
102018Test pattern compression for probabilistic circuitsChang, C.-M.; Yang, K.-J.; Li, J.C.-M.; Chen, H.; CHIEN-MO LI conference paper00
112018A new method for parameter estimation of high-order polynomial-phase signals.Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI journal article119
122017PSN-aware Circuit Test Timing Prediction using Machine LearningB. Liu; J. C.M. Li; CHIEN-MO LI journal article43
132017Physical-aware diagnosis of multiple interconnect defectsChen, P.-H.; Lee, C.-L.; Chen, J.-Y.; Chen, P.-W.; Li, J.C.-M.; CHIEN-MO LI conference paper10
142017Robust test pattern generation for hold-time faults in nanometer technologiesHo, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; Li, J.C.-M.; CHIEN-MO LI conference paper10
152017Automatic test pattern generationCheng, K.-T.T.; Wang, L.-C.; Li, H.; Li, J.C.-M.; CHIEN-MO LI book chapter00
162017Test Methodology for Dual-rail Asynchronous CircuitsHuang, K.-Y.; Shen, T.-Y.; Li, C.-M.; CHIEN-MO LI conference paper20
172017Physical-aware diagnosis of multiple interconnect defects.Chen, Po-Hao; Lee, Chi-Lin; Chen, Jing-Yu; Chen, Po-Wei; Li, James Chien-Mo; CHIEN-MO LI conference paper10
182017Test Pattern Compression for Probabilistic Circuits.Chang, Chih-Ming; Yang, Kai-Jie; Li, James Chien-Mo; Chen, Hung; CHIEN-MO LI conference paper00
192016A multicircuit simulator based on inverse jacobian matrix reuseLee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI journal article00
202016Test Pattern Modification for Average IR-Drop ReductionDing, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI journal article43
212016Power-supply-noise-aware timing analysis and test pattern regenerationHan, C.-Y.; Li, Y.-C.; Kan, H.-T.; Li, J.C.-M.; CHIEN-MO LI conference paper00
222015DR Scan: DR-scan: A Test Methodology for Dual-rail Asynchronous CircuitCHIEN-MO LI conference paper
232015TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal DefectsCHIEN-MO LI conference paper30
242015Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.Chiang, Kuan-Ying; Ho, Yu-Hao; Chen, Yo-Wei; Pan, Cheng-Sheng; Li, James Chien-Mo; CHIEN-MO LI conference paper60
252015The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent PreferencesFlahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI journal article21
262015Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET CircuitsChiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; Li, J.C.-M.; CHIEN-MO LI conference paper60
272014Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated CircuitsYI-CHANG LU ; CHIEN-MO LI journal article1611
282014Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible ElectronicsCHIEN-MO LI journal article1914
292014Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending EffectsI-CHUN CHENG ; CHIEN-MO LI journal article33
302014Transient IR-drop Analysis for At-speed Testing Using Representative Random WalkCHIEN-MO LI journal article32
312014Physical-aware Systematic Multiple Defect DiagnosisCHIEN-MO LI journal article52
322014Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D ICCHIEN-MO LI conference paper
332014GPU-Based Timing-Aware Test Generation for Small Delay DefectsCHIEN-MO LI conference paper40
342014Divide and Conquer Diagnosis for Multiple DefectsCHIEN-MO LI conference paper00
352014GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix ReuseCHIEN-MO LI conference paper
362014Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM TestingCHIEN-MO LI conference paper
372014A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending EffectsI-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI journal article51
382014GPU-based timing-aware test generation for small delay defects.Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI conference paper40
392013Compact Test Pattern Selection for Small Delay DefectCHIEN-MO LI journal article87
402013Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAMCHIEN-MO LI conference paper
412013Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPUCHIEN-MO LI conference paper
422013Test Pattern Modification for Average IR-drop ReductionCHIEN-MO LI conference paper
432013Testing Leakage Faults of Power TSV in 3D ICCHIEN-MO LI conference paper
442013Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic FunctionsCHIEN-MO LI conference paper10
452013Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous TriggeringCHIEN-MO LI journal article55
462013Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAMCHIEN-MO LI conference paper20
472013Test Generation of Path Delay Faults Induced by Defects in Power TSVCHIEN-MO LI conference paper10
482013Test Generation of Path Delay Faults Induced by Defects in Power TSV.Shih, Chi-Jih; Hsieh, Shih-An; Lu, Yi-Chang; Li, James Chien-Mo; Wu, Tzong-Lin; Chakrabarty, Krishnendu; CHIEN-MO LI conference paper10
492012Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending EffectsCHIEN-MO LI conference paper33
502012A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded CoresCHIEN-MO LI journal article4730
512012GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,CHIEN-MO LI conference paper100
522012Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,CHIEN-MO LI conference paper
532012Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,CHIEN-MO LI conference paper
542012Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling DesignsCHIEN-MO LI conference paper
552012Structural Reduction Techniques for Logic-Chain Bridging Fault DiagnosisCHIEN-MO LI journal article55
562012GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPGCHIEN-MO LI conference paper
5720123D IC test scheduling using simulated annealingCHIEN-MO LI conference paper60
582012Systematic Open Via Diagnosis Based on Physical FeaturesCHIEN-MO LI conference paper
592012Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional ICCHIEN-MO LI journal article40
602012Transient IR-drop Analysis for At-speed Testing Using Representative Random WalkCHIEN-MO LI conference paper32
612012Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,CHIEN-MO LI ; JIUN-LANG HUANG journal article00
622012An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder ExampleCHIEN-MO LI journal article22
632011A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality ObjectivesCHIEN-MO LI journal article1311
642011Compact test pattern Selection for Small Delay DefectsCHIEN-MO LI conference paper
652011Thermal-aware Test scheduling for 3D ICsCHIEN-MO LI conference paper
662011An At-speed Self-testable Technique for the High Speed Domino AdderCHIEN-MO LI conference paper10
672011An Asynchronous Design for Testability and Implementation in Thin-film Transistor TechnologyCHIEN-MO LI journal article66
682011Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During ScanCHIEN-MO LI conference paper20
692011Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chipsCHIEN-MO LI journal article22
702011Placement optimization of flexible TFT digital circuitsI-CHUN CHENG ; CHIEN-MO LI journal article33
712011Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domainsWu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; CHIEN-MO LI journal article21
722011Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese ChildrenFlahive, Mon-hsin Wang; Chuang, Ying-Chih; Li, Chien-Mo; CHIEN-MO LI journal article44
732011Placement optimization of flexible TFT digital circuitsLiu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI conference paper10
742011An accurate timing-aware diagnosis algorithm for multiple small delay defectsWEI-LI HSU; CHIEN-MO LI conference paper40
752010Static timing analysis for flexible TFT circuitsCHIEN-MO LI conference paper50
762010CSER: BISER-based concurrent soft-error resilienceCHIEN-MO LI ; JIUN-LANG HUANG conference paper20
772010DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-inCHIEN-MO LI ; Kao, Wei-Chung; Chuang, Wei-Shun; Lin, Hsiu-Ting; Li, J.C.-M.; Manquinho, V.journal article31
782010Row-LFSR-Column (RLC) Test Response Masking TechniqueCHIEN-MO LI conference paper
792010Method for adjusting clock domain during layout of integrated circuit and associated computer readable mediumCHIEN-MO LI patent
802010Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> TestingI-CHUN CHENG ; CHIEN-MO LI journal article21
812009Time-space test response compaction and diagnosis based on BCH codesWang, F.-M.; CHIEN-MO LI ; Wang, W.-C.; Li, J.C.-M.journal article00
822009Bridging Fault Diagnosis to Identify the Layer of Systematic DefectsCHIEN-MO LI conference paper30
832009Very-Low-Voltage Testing of Amorphous Silicon TFT CircuitsI-CHUN CHENG ; CHIEN-MO LI conference paper00
842009包含未知訊號之測試結果壓縮設計CHIEN-MO LI patent
852009Electronic Design AutomationCHIEN-MO LI book
862009Fault Modeling and Testing of Retention Flip-Flops in Low Power DesignsCHIEN-MO LI conference paper20
872009Test Response Compaction in the Presence of Many UnknownsCHIEN-MO LI conference paper
882009Transition Fault Diagnosis Using At-speed Test PatternsCHIEN-MO LI conference paper
892009BIST Design Optimization for Large-Scale Embedded Memory CoresCHIEN-MO LI conference paper70
902009Power Scan: DFT for Power Switches in VLSI DesignsCHIEN-MO LI conference paper
912009Fault Simulation and Test GenerationLi, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI book chapter10
922009Power scan: DFT for power switches in VLSI designs.Bai, Bing-Chuan; Li, Chien-Mo James; Kifli, Augusli; Tsai, Even; Wu, Kun-Cheng; CHIEN-MO LI conference paper00
932009Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.Shen, Shiue-Tsung; Liu, Wei-Hsiao; Ma, En-Hua; Li, James Chien-Mo; Cheng, I-Chun; CHIEN-MO LI conference paper10
942009Power scan: OFT for power switches in VLSI designsBai, B.-C.; Li, C.-M.; Kifli, A.; Tsai, E.; Wu, K.-C.; CHIEN-MO LI conference paper00
952008非同步電路可測試設計CHIEN-MO LI patent
962008可應用於軟性電子的TFT電路設計技術之開發-子計畫六:可應用於軟性電子數位電路測試及容錯技術之開發(2/3)李建模 report
972008Simultaneous capture and shift power reduction test pattern generator for scan testingCHIEN-MO LI journal article1010
982008A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT TechnologyCHIEN-MO LI conference paper
992008Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture ClocksCHIEN-MO LI conference paper
1002008An Asynchronous DFT Technique for TFT MacroelectronicsCHIEN-MO LI conference paper
1012008Survey of Scan Chain DiagnosisHuang, Y.; CHIEN-MO LI ; Guo, R; Cheng, W.T.; Li, J. C.-M.journal article4836
1022008Diagnosis of Logic-chain Bridging FaultsCHIEN-MO LI conference paper00
1032008Phase Noise Testing of Single Chip TV Tuners,CHIEN-MO LI conference paper00
1042008Diagnosis of Multiple Scan Chain Timing FaultsCHIEN-MO LI journal article88
1052008Effective and Economic Phase Noise Testing for Single-Chip TV TunersCHIEN-MO LI ; Li, J. C.-M.; Lin, P.-C.; Chiang, P.-C.; Pan, C.-M.; Tseng, C.W.journal article00
1062008Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise,CHIEN-MO LI conference paper10
1072008On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using A Hybrid Single-Capture Scheme for Testing Scan DesignsCHIEN-MO LI conference paper00
1082008IEEE 1500 Compatible Secure Test Wrapper For Embedded IP CoresCHIEN-MO LI conference paper40
1092008A two-level simultaneous test data and time reduction technique for SOCLiaw, Y.-T.; Bai, B.-C.; Li, J.C.M.; CHIEN-MO LI journal article1
1102007可應用於軟性電子的TFT電路設計技術之開發-子計畫六:可應用於軟性電子數位電路測試及容錯技術之開發(1/3)李建模 report
1112007Design and Chip Implementation of the Segment Weighted Random BIST for Low Power TestingCHIEN-MO LI journal article00
1122007奈米IC設計之前瞻電子設計自動化技術-子計畫六:在奈米製程下考量信號完整度之測試與診斷技術 (新制多年期第1年)李建模 report
1132007適用於建築結構監控之無線感測網路系統-子計畫二:超低功率可容錯及自測基頻通訊積體電路之研製(I)李建模 report
1142007Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and AnalysisCHIEN-MO LI journal article73
1152007Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter TechnologiesCHIEN-MO LI conference paper00
1162007Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction TechniqueCHIEN-MO LI conference paper00
1172006跳躍式掃描: 低功率可測試設計CHIEN-MO LI patent
1182006Jump Simulation: A Fast and Precise Scan Chain Diagnosis TechniqueCHIEN-MO LI conference paper250
1192006VLSI Test Principles and ArchitecturesCHIEN-MO LI book
1202006CRC BIST: A Low Peak Power Self TechniqueCHIEN-MO LI conference paper
1212006Logic and fault simulationHuang, J.-L.; Li, J.C.-M.; Walker, D.M.; CHIEN-MO LI book chapter00
1222005Diagnosis of Resistive and Stuck-open Defects in Digital CMOS ICCHIEN-MO LI journal article3523
1232005Diagnosis of Multiple Hold-time and Setup-time Faults in Scan ChainsCHIEN-MO LI journal article2223
1242005掃描鏈中多重時間錯誤之診斷李建模 report
1252005Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan ChainsCHIEN-MO LI ; Lin, Hung-Mao; Li, J.C.M.conference paper100
1262005子計畫五:具有自我測試功能之低功率基頻數位收發機電路 設計(1/2)李建模 report
1272005Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan ChainsCHIEN-MO LI journal article3331
1282005Jump Scan: A DFT Technique for Low Power Testing,CHIEN-MO LI conference paper360
1292005Diagnosis of Timing Faults in Scan Chains Using Single Excitation PatternsCHIEN-MO LI journal article55
1302005A Two-level Test Data Compression and Test Time Reduction Technique for SOCCHIEN-MO LI conference paper
1312005Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power TestingCHIEN-MO LI conference paper10
1322005Effective and Economic Phase Noise Testing for Single Chip TV TunersCHIEN-MO LI conference paper
1332004單晶片電視調諧器之經濟有效測試方法李建模 report
1342004A Design for Testability Technique for Low Power Delay Fault TestingCHIEN-MO LI journal article24
1352004Design and Implementation of a Low Power Delay Fault Built-in Self Test TechniqueCHIEN-MO LI conference paper
1362004Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation PatternsCHIEN-MO LI conference paper
1372004ELF-Murphy Data on Defects and Test SetsCHIEN-MO LI conference paper410
1382004具有內建自我測試功能之5GHz超低功率無線通訊系統之研製─子計畫五:具有自我測試功能之低功率基頻數位收發機電路設計李建模 report
1392002Experimental Results for Slow Speed TestingCHIEN-MO LI conference paper60
1402002Diagnosis for Sequence Dependent ChipsCHIEN-MO LI conference paper430
1412001Pseudo Random Testing Theoretical Models vs. Real DataCHIEN-MO LI conference paper
1422001Diagnosis of Tunneling OpensCHIEN-MO LI conference paper20
1432001Testing for Resistive and Stuck OpensCHIEN-MO LI conference paper1170
1442000Testing for tunneling opens.Li, Chien-Mo James; McCluskey, Edward J.; CHIEN-MO LI conference paper00
1451998IDDQ data analysis using current signatureLi, J.C.M.; McCluskey, E.J.; CHIEN-MO LI conference paper110
1461998Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.Chang, Jonathan T.-Y.; Tseng, Chao-Wen; Li, Chien-Mo James; Purtell, Mike; McCluskey, Edward J.; CHIEN-MO LI conference paper00