第 1 到 103 筆結果,共 103 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2022 | Sub-resolution assist feature generation with reinforcement learning and transfer learning | Liu, Guan Ting; Tai, Wei Chen; Lin, Yi Ting; HUI-RU JIANG ; Shiely, James P.; PU-JEN CHENG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2 | 2022 | Timing macro modeling with graph neural networks | Chang, Kevin Kai Chun; Chiang, Chun Yao; Lee, Pei Yu; HUI-RU JIANG | Proceedings - Design Automation Conference | 3 | 0 | |
3 | 2022 | Novel Methodology for SRAF Placement over a Machine Learning Generated Probability Map | Lin, Yi Ting; Tseng, Sean Shang En; HUI-RU JIANG ; Shiely, James P. | Proceedings of SPIE - The International Society for Optical Engineering | 0 | 0 | |
4 | 2022 | Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories | Lin, Li Heng; Wang, Kuan Chun; Lee, Ying Hua; Lin, Kai En; CHUNG-WEI LIN ; HUI-RU JIANG | IEEE Intelligent Vehicles Symposium, Proceedings | 0 | 0 | |
5 | 2022 | Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets | Tsou T.-L; CHUNG-WEI LIN ; HUI-RU JIANG | Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 | 0 | 0 | |
6 | 2022 | Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering | Chen Y.-S; HUI-RU JIANG | Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 | 1 | 0 | |
7 | 2022 | Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines | Lu C.-P; HUI-RU JIANG ; Yang C.-W. | Proceedings of the International Symposium on Physical Design | 0 | 0 | |
8 | 2021 | Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials | Lin Y.-T; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
9 | 2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
10 | 2021 | DATC RDF-2021: Design Flow and Beyond | Chen J; Jung J; Kahng A.B; Kim S; Kravets V.N; Li Y.-L; Varadarajan R; Woo M.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 7 | 0 | |
11 | 2021 | OpenMPL: An Open-Source Layout Decomposer | Li W; Ma Y; Sun Q; Zhang L; Lin Y; Jiang I.H.-R; Yu B; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
12 | 2021 | Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles | Lin S.-C; Kung C.-C; Lin L; CHUNG-WEI LIN ; HUI-RU JIANG | IEEE Vehicular Technology Conference | 0 | 0 | |
13 | 2021 | Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval | Tseng S.S.-E; Shiely J.P.; HUI-RU JIANG | Proceedings - Design Automation Conference | 2 | 0 | |
14 | 2020 | Fast and accurate wire timing estimation on tree and non-tree net structures | Cheng, H.-H.; Ou, O.; HUI-RU JIANG | Proceedings - Design Automation Conference | 13 | 0 | |
15 | 2020 | Late breaking results: Design dependent mega cell methodology for area and power optimization | Lu, C.-P.; Yang, C.-W.; HUI-RU JIANG | Proceedings - Design Automation Conference | 0 | 0 | |
16 | 2020 | Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability | Yu, S.-J.; Kao, C.-C.; Huang, C.-H.; HUI-RU JIANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 3 | 0 | |
17 | 2020 | Routing topology and time-division multiplexing co-optimization for multi-FPGA systems | Lin, T.-W.; Tai, W.-C.; Lin, Y.-C.; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
18 | 2020 | A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles | Lin S.-C; Hsu H; Lin Y.-T; CHUNG-WEI LIN ; Liu C.; HUI-RU JIANG | IEEE Intelligent Vehicles Symposium, Proceedings | 4 | 0 | |
19 | 2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
20 | 2020 | DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design | Chen J; Jiang I.H.-R; Jung J; Kahng A.B; Kravets V.N; Li Y.-L; Lin S.-T; Woo M.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
21 | 2020 | Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance | Huang X.-X; Chen H.-C; Wang S.-W; Jiang I.H.-R; Chou Y.-C; Tsai C.-H.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
22 | 2019 | Efficient search of layout hotspot patterns for matching SEM images using multilevel pixelation | Sean Shang-En Tseng; Wei-Chun Chang; Iris Hui-Ru Jiang; Jun Zhu; James P. Shiely; HUI-RU JIANG ; 江蕙如 | SPIE Advanced Lithography Conference (AL-2019) | 6 | 0 | |
23 | 2019 | Novel guiding template and mask assignment for DSA-MP hybrid lithography using multiple BCP materials | Yi-Ting Lin; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如 | 56th ACM/IEEE Design Automation Conference (DAC-2019) | 5 | 0 | |
24 | 2019 | Graceful register clustering by effective mean shift algorithm for power and timing balancing | Ya-Chu Chang; Tung-Wei Lin; Iris Hui-Ru Jiang; Gi-Joon Nam; HUI-RU JIANG ; 江蕙如 | 28th ACM International Symposium on Physical Design (ISPD-2019) | 3 | 0 | |
25 | 2019 | Multiple patterning layout compliance with minimizing topology disturbance and polygon displacement | Hua-Yu Chang; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如 | 28th ACM International Symposium on Physical Design (ISPD-2019) | 1 | 0 | |
26 | 2019 | iClaire: A Fast and General Layout Pattern Classification Algorithm with Clip Shifting and Centroid Recreation | Chang, W.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
27 | 2019 | DATC RDF-2019: Towards a complete academic reference design flow | Chen, J.; Jiang, I.H.-R.; Jung, J.; Kahng, A.B.; Kravets, V.N.; Li, Y.-L.; Lin, S.-T.; Woo, M.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
28 | 2019 | Openmpl: An open source layout decomposer: Invited paper | Li, W.; Ma, Y.; Sun, Q.; Lin, Y.; Jiang, I.H.-R.; Yu, B.; Pan, D.Z.; HUI-RU JIANG | Proceedings of International Conference on ASIC | |||
29 | 2018 | DATC RDF: An academic flow from logic synthesis to detailed routing | Jinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam; HUI-RU JIANG ; 江蕙如 | IEEE/ACM International Conference on Computer Aided Design (ICCAD-2018) | 11 | 0 | |
30 | 2018 | iTimerM: A compact and accurate timing macro model for efficient hierarchical timing analysis | Pei-Yu Lee; Iris Hui-Ru Jiang; HUI-RU JIANG | accepted by ACM Transactions on Design Automation of Electronic Systems (ACM TODAES) | 2 | 3 | |
31 | 2018 | COSAT: Congestion, obstacle, and slew Aware tree construction for multiple power domain design | Chien-Pang Lu; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如 | 55th ACM/EDAC/IEEE Design Automation Conference (DAC-2018) | 1 | 0 | |
32 | 2018 | OWARU: Free space-aware timing-driven incremental placement with critical path smoothing | Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) | 7 | 5 | |
33 | 2018 | Timing Macro Modeling for Efficient Hierarchical Timing Analysis. | Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG | 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 | |||
34 | 2018 | Recent research and challenges in multiple patterning layout decomposition | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | |||
35 | 2018 | FastPass: Fast timing path search for generalized timing exception handling | Lee, P.-Y.; Jiang, I.H.-R.; Chen, T.-C.; HUI-RU JIANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
36 | 2017 | iTimerM: Compact and accurate timing macro modeling for hierarchical timing analysis | Pei-Yu Lee; Iris Hui-Ru Jiang; Ting-You Yang; HUI-RU JIANG ; 江蕙如 | 26th ACM International Symposium on Physical Design (ISPD-2017) | |||
37 | 2017 | DRC-based hotspot detection considering edge tolerance and incomplete specification | Yen-Ting Yu; Hui-Ru Jiang; Yumin Zhang; Charles C. Chiang; HUI-RU JIANG ; 江蕙如 | ||||
38 | 2017 | iClaire: A fast and general layout pattern classification algorithm | Wei-Chun Chang; Iris Hui-Ru Jiang; Yen-Ting Yu; Wei-Fang Liu; HUI-RU JIANG ; 江蕙如 | 54th ACM/EDAC/IEEE Design Automation Conference (DAC-2017) | 15 | 0 | |
39 | 2017 | Multiple patterning layout decomposition considering complex coloring rules and density balancing | Iris Hui-Ru Jiang; Hua-Yu Chang; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) | 12 | 9 | |
40 | 2017 | DATC RDF: Robust design flow database | Jinwook Jung; Pe-Yu Lee; Yan-Shiun Wu; Nima Darav; Iris Hui-Ru Jiang; Gi-Joon Nam; Victor N. Kravets; Laleh Behjat; Yih-Lang Li; HUI-RU JIANG ; 江蕙如 | IEEE/ACM International Conference on Computer Aided Design (ICCAD-2017) | |||
41 | 2017 | Power and area efficient hold time fixing by free metal segment allocation | Wei-Lun Chiu; Iris Hui-Ru Jiang; Chien-Pang Lu; Yu-Tung Chang; HUI-RU JIANG ; 江蕙如 | 54th ACM/EDAC/IEEE Design Automation Conference (DAC-2017) | 1 | 0 | |
42 | 2017 | DATC RDF: Robust design flow database: Invited paper | Jung, J.; Lee, P.-Y.; Wu, Y.-S.; Darav, N.K.; Jiang, I.H.-R.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; Nam, G.-J.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
43 | 2017 | Fast low power rule checking for multiple power domain design. | Lu, Chien-Pang; HUI-RU JIANG | Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017 | |||
44 | 2017 | iTimerM: Compact and accurate timing macro modeling for efficient hierarchical timing analysis | Lee, P.-Y.; Jiang, I.H.-R.; Yang, T.-Y.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
45 | 2016 | Analytical clustering score with application to post-placement register clustering | Chang Xu; Guojie Luo; Peixin Li; Yiyu Shi; Iris Hui-Ru Jiang; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems (ACM TODAES) | 1 | 2 | |
46 | 2016 | GasStation: Power and area efficient buffering for multiple power domain design | Lu, C.-P.; Jiang, I.H.-R.; Hsu, C.-H.; HUI-RU JIANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | |||
47 | 2016 | Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits | Schlichtmann, U.; Hashimoto, M.; Jiang, I.H.-R.; Li, B.; HUI-RU JIANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
48 | 2016 | ITimerC 2.0: Fast incremental timing and CPPR analysis | Lee, P.-Y.; Jiang, I.H.-R.; Li, C.-R.; Chiu, W.-L.; Yang, Y.-M.; HUI-RU JIANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | |||
49 | 2016 | Multiple patterning layout decomposition considering complex coloring rules | Chang, H.-Y.; HUI-RU JIANG | Proceedings - Design Automation Conference | |||
50 | 2016 | OpenDesign flow database: The infrastructure for VLSI design and design automation research | Jung, J.; Jiang, I.H.-R.; Nam, G.-J.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
51 | 2016 | OWARU: Free space-aware timing-driven incremental placement | Jung, J.; Nam, G.-J.; Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
52 | 2016 | Resource-aware functional ECO patch generation | Cheng, A.-C.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | |||
53 | 2015 | Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations | Jiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
54 | 2015 | Analytical Clustering score with application to post-placement multi-bit flip-flop merging | Xu, C.; Li, P.; Luo, G.; Shi, Y.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
55 | 2015 | Feature detection for image analytics via FPGA acceleration | Chang, H.-Y.; Jiang, I.H.-R.; Hofstee, H.P.; Jamsek, D.; Nam, G.-J.; HUI-RU JIANG | IBM Journal of Research and Development | |||
56 | 2015 | Machine-learning-based hotspot detection using topological classification and critical feature extraction | Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
57 | 2015 | DRC-based hotspot detection considering edge tolerance and incomplete specification | Yu, Y.-T.; Jiang, I.H.-R.; Zhang, Y.; Chiang, C.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
58 | 2015 | ITimerC: Common path pessimism removal using effective reduction methods | Yang, Y.-M.; Chang, Y.-W.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
59 | 2015 | Criticality-dependency-aware timing characterization and analysis | Yang, Y.-M.; Tam, K.H.; HUI-RU JIANG | Proceedings - Design Automation Conference | |||
60 | 2014 | Functional ECO using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Design Automation Conference | 1 | 0 | |
61 | 2014 | PushPull: Short-path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
62 | 2014 | The overview of 2014 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 | |||
63 | 2014 | Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog | Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems | |||
64 | 2013 | ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
65 | 2013 | Machine-learning-based hotspot detection using topological classification and critical feature extraction | Yu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG | Proceedings - Design Automation Conference | |||
66 | 2013 | PushPull: Short path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
67 | 2013 | Pulsed-latch replacement using concurrent time borrowing and clock gating | Chang, C.-L.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
68 | 2013 | FF-bond: Multi-bit flip-flop bonding at placement | Tsai, C.-C.; Shi, Y.; Luo, G.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
69 | 2013 | The overview of 2013 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | |||
70 | 2012 | WiT: Optimal wiring topology for electromigration avoidance | Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 21 | 19 | |
71 | 2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
72 | 2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
73 | 2012 | Generic integer linear programming formulation for 3D IC partitioning | Lee, W.-Y.; Jiang, I.H.-R.; Mei, T.-W.; HUI-RU JIANG | Journal of Information Science and Engineering | |||
74 | 2012 | Novel pulsed-latch replacement based on time borrowing and spiral clustering | Chang, C.-L.; Jiang, I.H.-R.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, A.S.-H.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
75 | 2012 | INTEGRA: Fast multibit flip-flop clustering for clock power saving | Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
76 | 2012 | Accurate process-hotspot detection using critical design rule extraction | Yu, Y.-T.; Chan, Y.-C.; Sinha, S.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG | Proceedings - Design Automation Conference | |||
77 | 2012 | Reliability-driven power/ground routing for analog ICs | Lin, J.-W.; Ho, T.-Y.; HUI-RU JIANG | ACM Transactions on Design Automation of Electronic Systems | |||
78 | 2012 | ECOS: Stable matching based metal-only ECO synthesis | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |||
79 | 2012 | Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. | Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang; HUI-RU JIANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | |||
80 | 2011 | Simultaneous functional and timing ECO. | Chang, Hua-Yu; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 17 | 0 | |
81 | 2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
82 | 2011 | 3DICE: 3D IC cost evaluation based on fast tier number estimation | Chan, C.-C.; Yu, Y.-T.; HUI-RU JIANG | Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 | |||
83 | 2011 | INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs | Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
84 | 2011 | Recent research development in metal-only ECO | Tan, C.-Y.; HUI-RU JIANG | Midwest Symposium on Circuits and Systems | |||
85 | 2010 | Live demo: ECOS 1.0: A metal-only ECO synthesizer | Jiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG | ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems | |||
86 | 2010 | Analog placement and global routing considering wiring symmetry | Yang, Y.-M.; HUI-RU JIANG | Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010 | |||
87 | 2010 | Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles | Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | |||
88 | 2010 | Simultaneous voltage island generation and floorplanning | Li, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG | Proceedings - IEEE International SOC Conference, SOCC 2010 | |||
89 | 2009 | Generic integer linear programming formulation for 3D IC partitioning | HUI-RU JIANG | Proceedings - IEEE International SOC Conference, SOCC 2009 | |||
90 | 2009 | POSA: Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | Proceedings - IEEE International Symposium on Circuits and Systems | |||
91 | 2009 | Matching-based minimum-cost spare cell selection for design changes. | Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi; HUI-RU JIANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | |||
92 | 2009 | VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and power | Lee, W.Y.; HUI-RU JIANG | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI | |||
93 | 2008 | Topology generation and floorplanning for low power application-specific network-on-chips | Lee, W.-Y.; HUI-RU JIANG | 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT | |||
94 | 2008 | Unification of obstacle-avoiding rectilinear steiner tree construction | Jiang, I.H.-R.; Lin, S.-W.; Yu, Y.-T.; HUI-RU JIANG | 2008 IEEE International SOC Conference, SOCC | |||
95 | 2008 | Configurable rectilinear steiner tree construction for SoC and nano technologies | Jiang, I.H.R.; Yu, Y.T.; HUI-RU JIANG | 26th IEEE International Conference on Computer Design 2008, ICCD | |||
96 | 2008 | Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | 26th IEEE International Conference on Computer Design 2008, ICCD | |||
97 | 2007 | Performance constraints aware voltage Islands generation in SoC floorplan design | Lu, M.-C.; Wu, M.-C.; Chen, H.-M.; HUI-RU JIANG | 2006 IEEE International Systems-on-Chip Conference, SOC | |||
98 | 2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 2 | |
99 | 2004 | Simultaneous Floorplan and Buffer-Block Optimization | HUI-RU JIANG ; YAO-WEN CHANG ; Jou, Jing-Yang; Chao, Kai-Yuan | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 2 | |
100 | 2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
101 | 2002 | Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. | Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002 | 1 | 0 | |
102 | 2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
103 | 2000 | Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Trans. on CAD of Integrated Circuits and Systems | 49 | 40 |