DSpace 集合:
https://scholars.lib.ntu.edu.tw/handle/123456789/59259
2024-03-28T17:13:34ZGraph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology
https://scholars.lib.ntu.edu.tw/handle/123456789/636610
標題: Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology
作者: Chen, Wei Hsu; YAO-WEN CHANG
摘要: Two-dimensional directed self-assembly (2D-DSA) is an emerging lithography technology for advanced process nodes. We can determine the orientations of double posts to guide block copolymers to form feasible 2D guiding template patterns by the 2D-DSA process. This paper presents the first work to handle the 2D-DSA simultaneous placement and routing problem. We first propose a novel graph to model feasible guiding templates with a constant-time update scheme for each double-post assignment. Based on a graph model, we then present an algorithm for 2D-DSA simultaneous placement and routing, with a broadcast-based cost function for 2D-DSA cell placement and a graph-based scheme for DSA-compliant routing. Finally, we employ a strongly effective region property to minimize the cuts in the final layout. Experimental results show that our algorithm can efficiently generate a 2D-DSA placement and routing solution with high routability and a low cut number.2023-01-01T00:00:00ZAny-Angle Routing for Redistribution Layers in 2.5D IC Packages
https://scholars.lib.ntu.edu.tw/handle/123456789/636609
標題: Any-Angle Routing for Redistribution Layers in 2.5D IC Packages
作者: Chung, Min Hsuan; Chuang, Je Wei; YAO-WEN CHANG
摘要: Redistribution layers (RDLs) are widely applied for signal transmissions in advanced packages. Traditional redistribution layer (RDL) routers use only 90- and 135-degree turns for routing. With technological advances, routing in RDLs can be any obtuse angle, leading to larger routing solution spaces and shorter total wirelength. This paper proposes the first any-angle routing algorithm in the literature for multiple RDLs. We first give a novel global routing algorithm with accurate routing resource estimation. A multi-net access point adjustment method is then proposed based on dynamic programming and our partial net separation scheme. Finally, we develop an efficient tile routing algorithm to obtain valid routes with fixed access points. Experimental results show that our algorithm can achieve a 15.7% shorter wirelength compared with a traditional RDL router.2023-01-01T00:00:00ZLate Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
https://scholars.lib.ntu.edu.tw/handle/123456789/636608
標題: Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
作者: Chen, Yan Jen; Chen, Yan Syuan; Tseng, Wei Che; Chiang, Cheng Yu; Lo, Yu Hsiang; YAO-WEN CHANG
摘要: This paper proposes a high-quality 3D placement algorithm to determine the positions of standard cells and inter-die vias to optimize wirelength considering multiple manufacturing technologies for different dies. The algorithm consists of three major novel techniques: (1) a multi-technologies weighted-average (MTWA) wirelength model, (2) a weighted inter-die-connection cost controlling the net-degree distribution of the cut set, and (3) a via-cell co-optimization technique to further improve the quality of placement solutions. Compared with the winners at the 2022 CAD Contest at ICCAD on 3D Placement with D2D Vertical Connections, our placer achieves the best results for all nontrivial cases.2023-01-01T00:00:00ZA Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints
https://scholars.lib.ntu.edu.tw/handle/123456789/636607
標題: A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints
作者: Liu, Qinghai; Lin, Disi; Chen, Chuandong; He, Huan; Chen, Jianli; YAO-WEN CHANG
摘要: Escape routing is a critical problem in PCB routing, and its quality greatly affects the PCB design cost. Unlike the traditional escape routing that works mainly for the BGA package with unique line width and space, this paper presents a high-performance escape routing algorithm to handle problems with variable design rules and manual constraints, including variable line widths/spaces, the neck mode of wires, and the pad entry for differential pairs. We first propose a novel obstacle-avoiding method to project pins to the boundary and construct a channel projection graph. We then construct a bi-projection graph and propose a matching-based hierarchical sequencing algorithm to consider manual constraints. We perform global routing for each pin/differential pair by congestion-avoiding path initialization and rip-up and reroute path optimization. Finally, we complete detailed routing in every face, ensuring the wire angle and pad entry constraints. Experimental results show that our algorithm can achieve 100% routability without any design rule violation for all given industrial PCB instances, while two state-of-the-art routers cannot complete routing.2023-01-01T00:00:00Z