https://scholars.lib.ntu.edu.tw/handle/123456789/116396
標題: | A power-aware SWDR cell for reducing cache write power | 作者: | Chang, Yen-Jen Yang, Chia-Lin Lai, Feipei |
關鍵字: | Bridge circuits; Circuit stability; Data mining; Energy consumption; Microprocessors; Permission; Random access memory; Tail; Voltage; Writing | 公開日期: | 2003 | 起(迄)頁: | 14-17 | 來源出版物: | 2003 International Symposium on Low Power Electronics and Design | 摘要: | Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%-92% reduction in average cache write power dissipated in bitlines. © 2003 ACM. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/200704191002950 http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002950/1/01231826.pdf |
其他識別: | N/A | DOI: | 10.1109/LPE.2003.1231826 | SDG/關鍵字: | Bridge circuits; Cells; Cytology; Data mining; Electric potential; Energy utilization; Hand held computers; Microprocessor chips; Power electronics; Power management; Random access storage; Static random access storage; Technical writing; Cache power consumption; Circuit stability; Critical component; High performance processors; Low power techniques; Permission; Random access memory; Tail; Low power electronics |
顯示於: | 資訊工程學系 |
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