https://scholars.lib.ntu.edu.tw/handle/123456789/118211
標題: | Cache Leakage Control Mechanism for Hard Real-Time Systems | 作者: | Chi, Jaw-Wei CHIA-LIN YANG Chen, Yi-Jung Chen, Jien-Jia |
公開日期: | 2007 | 起(迄)頁: | 248-256 | 來源出版物: | 2007 international conference on Compilers, architecture, and synthesis for embedded systems | 摘要: | Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transistor budget, several leakage control policies have been proposed to reduce cache leakage. However, these policies introduce performance unpredictability thereby not suitable for hard real-time applications that require the timing constraint is met in all cases. In this paper, we propose the first approach to apply existing low leakage circuit techniques on hard real-time applications. The proposed timing-aware cache leakage control mechanism exploits task slack time to turn cache lines into the low-leakage state provided that the timing constraint is met. The experimental results show that the proposed cache leakage control policy achieves comparable leakage reduction to the leakage control policy that aggressively turn cache lines into low-leakage modes without considering the timing constraint. Copyright 2007 ACM. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/232559 http://ntur.lib.ntu.edu.tw/bitstream/246246/232559/-1/07.pdf https://scholars.lib.ntu.edu.tw/handle/123456789/487780 https://doi.org/10.1145/1289881.1289924 |
DOI: | 10.1145/1289881.1289924 | SDG/關鍵字: | Energy policy; Microprocessor chips; Program processors; Transistors; Cache leakage control policy; Hard real-time systems; Real time systems |
顯示於: | 資訊工程學系 |
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