https://scholars.lib.ntu.edu.tw/handle/123456789/122012
標題: | GHz 系統中差模對傳輸線的訊號完整度分析 (2/3) Signal Integrity for Differential Signaling in Gigahertz Systems (2/3) |
作者: | 吳瑞北 | 關鍵字: | 差模傳輸線;接地雜訊;多重轉折蛇 狀延遲線;螺旋延遲線;連通柱;信號完整度;Differential signaling;ground bounce;serpentine delay line;flat spiral delay line;via;Signal integrity | 公開日期: | 31-七月-2004 | 出版社: | 臺北市:國立臺灣大學電信工程學研究所 | 摘要: | 本計畫延續上一年的研究工作,分為三個 重點,分別研究差模對傳輸線對於跨越窄開槽 所引發之彈地雜訊,差模傳輸延遲線的效應, 及多層板構裝結構中連通柱等效集總電路模 型幾何參數正規化設計圖表之完成。 在第一部份中,我們探討差模傳輸線的重 要特性參數(耦合係數、信號的上升時間、介 電係數、與兩信號的skew)對於差模信號跨越 槽線所引發接地雜訊的影響,並對差模傳輸線 抑制接地雜訊的現象,建立簡易說明模型,最 後也做了實驗來驗證其模擬分析方法與模型 的正確性。 在第二部分中,我們針對為了信號時序同 步的問題而常使用的差模傳輸多重轉折蛇狀 延遲線與其改良型的差模傳輸平面螺旋延遲 線,探討其時域反射、穿透波形與其眼狀圖。 第三部分則是以利用HFSS 做全波的模 擬,來分析各種不同參數變化的連通柱等效集 總電路模型,並繪出等效模型電容與電感刻度 規一化的參數設計圖表。另外也分析其多層結 構連通柱的時域模擬波形。 In this year, the project emphasizes three parts: to investigate the ground bounce induced by differential lines crossing the narrow slotline, to find the delay line effect on the differential transmission lines, and to establish the normalized design table of lumped element equivalent circuit model parameters of the through-hole vias in multi-layered packaging environment. For part one, several important parameters (coupling factor, rising time, dielectric constant, skew) of differential signaling are changed to find the influence on ground bounce. A simple model is built and verified to characterize how the differential microstrip lines can help minimize the ground bounce. An experimental setup is devised to demonstrate the noise coupling between signal lines due to the slot-induced ground bounce and the significant reduction by the employment of differential signaling. Favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach. For part two, a simple simulation scheme for the eye diagrams of differential delay lines are presented. Based on the measured and simulated TDR or TDT waveform, the eye- of both the serpentine and flat spiral delay lines are simulated and analyzed. For part three, the through-hole vias in multi-layered packaging are divided into several building sub-structures. The parameters of the sub-structure are changed one by one to simulate the lumped equivalent circuit model by the full wave simulator HFSS. The extracted inductance and capacitance values versus the sub-structure parameters are drawn and from which, some empirical formulae are obtained. After an extensive analysis, some dimensionless design charts are given for easy use in practical applications. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/20284 | 其他識別: | 922213E002036 | Rights: | 國立臺灣大學電信工程學研究所 |
顯示於: | 電信工程學研究所 |
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922213E002036.pdf | 349.23 kB | Adobe PDF | 檢視/開啟 |
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