|Title:||A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle||Authors:||Han, Sung-Rung
|Keywords:||Duty-cycle presetting;fast locking;pulsewidth control loop (PWCL);switched charge pump;voltage-difference- to-digital converter||Issue Date:||Mar-2004||Journal Volume:||VOL. 39||Journal Issue:||NO. 3||Start page/Pages:||-||Source:||IEEE JOURNAL OF SOLID-STATE CIRCUITS||Abstract:||
A 500-MHz–1.25-GHz fast-locking pulsewidth control
loop (PWCL) with presettable duty cycle is realized in 0.35- m
CMOStechnology. The proposed voltage-difference-to-digital converter
and switched charge pump circuits reduce the lock time of
a conventional PWCL. Compared with the conventional PWCL,
the proposed circuit can reduce the lock time by a factor of 2.58. A
method to preset the duty cycle of the output clock is also described.
Circuit measurements verify that the duty cycle of the output clock
can be adjusted from 35% to 70% in steps of 5%.
|Appears in Collections:||電機工程學系|
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