https://scholars.lib.ntu.edu.tw/handle/123456789/148108
標題: | Fault-tolerant serial-parallel multiplier | 作者: | LIANG-GEE CHEN Chen, T.H. |
公開日期: | 七月-1991 | 卷: | 138 | 期: | 4 | 起(迄)頁: | 276 - 280 | 來源出版物: | IEE Proceedings E: Computers and Digital Techniques | 摘要: | The paper presents a novel fault-tolerant circuit design using a time-redundancy method for a serial-parallel multiplier, which is useful in DSP applications with serial data transmission. It utilises the RECO (Recomputing with Circularly shifted Operands) technique to detect errors concurrently. A simple OR-gate based circuit is used as the location table to identify faulty bit-slice pairs. The reconfiguration technique is then introduced to bypass the potential faulty bit-slices. This design can have the maximum detectable error region (≅n/2 bits), without appending extra computing elements. The latency from error detection to location is only about two clock cycles, i.e. almost real-time detecting can be achieved. Pipelined timing for two computations is illustrated. The analyses of performance and complexity are described. The results show that this is an efficient design methodology for fault-tolerant multiplication with serial data. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032509 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0026190265&doi=10.1049%2fip-e.1991.0036&partnerID=40&md5=f663d148923606b539a2bd07f898f10d |
ISSN: | 01437062 | 其他識別: | 1350-2387 | DOI: | 10.1049/ip-e.1991.0036 | SDG/關鍵字: | Computer systems, Digital--Fault tolerant capability; Data Transmission--Computer Applications; Logic devices--Gates; Signal processing--Digital techniques; Fault-Tolerant Serial-Parallel Multiplier; Faulty Bit-Slice Pairs Identification; OR-Gate Based Circuit; Recomputing With Circularly Shifted Operands (RECO); Serial Data Transmission; Time-Redundancy Method; Computers |
顯示於: | 電機工程學系 |
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00081907.pdf | 437.06 kB | Adobe PDF | 檢視/開啟 |
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