https://scholars.lib.ntu.edu.tw/handle/123456789/151699
標題: | A hybrid morphology processing units architecture for real-time video segmentation systems | 作者: | SHAO-YI CHIEN Huang, Yu-Wen Ma, Shyh-Yih LIANG-GEE CHEN |
公開日期: | 2001 | 卷: | 5 | 起(迄)頁: | 275-278 | 來源出版物: | ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings | 會議論文: | 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 | 摘要: | In this paper, we propose a hybrid morphology processing units architecture for real-time video segmentation systems. It contains two parts: a gray-level part and a binary part. A partial-result-reuse technique is applied to reduce the hardware cost of gray-level part. For the target of high throughput and flexibility, the binary part is implemented with a programmable PE array. Simulation shows the proposed hardware architecture is efficient in both hardware complexity and memory organization. © 2001 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035016748&doi=10.1109%2fiscas.2001.922038&partnerID=40&md5=85b6f107ef9d0381c091990fea019da1 http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021242/1/00922038.pdf |
DOI: | 10.1109/ISCAS.2001.922038 | SDG/關鍵字: | Computer architecture; Image segmentation; Morphology; Video signal processing; Algorithms; Computer architecture; Computer hardware; Computer simulation; Program processors; Real time systems; Video signal processing; Hardware architecture; Hardware complexity; Hardware cost; High throughput; Hybrid morphology; Memory organizations; Partial result reuse; Real-time video segmentation; Real time systems; Image segmentation; Video segmentation systems |
顯示於: | 電機工程學系 |
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