https://scholars.lib.ntu.edu.tw/handle/123456789/153386
標題: | VLSI architecture for radix-2k Viterbi decoding with transpose algorithm | 作者: | Lee, Wen-Ta Chen, Thou-Ho LIANG-GEE CHEN |
公開日期: | 六月-1995 | 起(迄)頁: | 219 - 223 | 來源出版物: | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | 會議論文: | Proceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications | 摘要: | The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for radix-2k Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM has been developed. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032063 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029509877&partnerID=40&md5=5a062c3e75338ef1101489467bcd1329 |
其他識別: | N/A | DOI: | 10.1109/VTSA.1995.524667 | SDG/關鍵字: | Algorithms; Computation theory; Computational complexity; Computer architecture; Convolutional codes; Data storage equipment; Decoding; Modulation; Shift registers; VLSI circuits; Decoder; Interconnection routing complexity; Permutation function; Radix; Transpose path metric; Viterbi decoder; Data communication equipment |
顯示於: | 電機工程學系 |
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