https://scholars.lib.ntu.edu.tw/handle/123456789/154800
標題: | Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder | 作者: | Chen, Tung-Chien SHAO-YI CHIEN Huang, Yu-Wen Tsai, Chen-Han Chen, Ching-Yeh Chen, To-Wei LIANG-GEE CHEN |
關鍵字: | ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Joint Video Team (JVT); Single-chip video encoder; Very large-scale integration (VLSI) architecture | 公開日期: | 2006 | 卷: | 16 | 期: | 6 | 起(迄)頁: | 673-688 | 來源出版物: | IEEE Transactions on Circuits and Systems for Video Technology | 摘要: | H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency. © 2006 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33746358201&doi=10.1109%2fTCSVT.2006.873163&partnerID=40&md5=4ff552272c9757fdc1bad5434892fb72 http://scholars.lib.ntu.edu.tw/handle/123456789/321236 http://ntur.lib.ntu.edu.tw/bitstream/246246/141461/1/49.pdf |
ISSN: | 10518215 | DOI: | 10.1109/TCSVT.2006.873163 | SDG/關鍵字: | ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Joint Video Team (JVT); Single-chip video encoder; Very large-scale integration (VLSI) architecture; Computational complexity; Computer architecture; Computer hardware; Logic gates; Motion estimation; Parallel processing systems; Real time systems; Static random access storage; Image coding |
顯示於: | 電機工程學系 |
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