https://scholars.lib.ntu.edu.tw/handle/123456789/173514
標題: | 子計劃六:可重組化運算之測試設計(I) | 作者: | 黃俊郎 | 關鍵字: | 微處理器;自我測試;結構性錯誤;microprocessor;self-testing;structural faults | 公開日期: | 31-七月-2003 | 出版社: | 臺北市:國立臺灣大學電子工程學研究所 | 摘要: | 在現在的電子產業中,微處理器(microprocessor)的重要性無庸置疑。除了被用來 當做電腦的中央處理單元(central processing unit, CPU)外,也是許多電子消費產品 的大腦。自Intel 4004 問世以來至今,隨著微處理器在晶片面積、性能與複雜度各方 面的快速成長,其設計驗證(design verification)與生產測試(manufacturing testing)的 難度也隨之增加。 本計劃的研究主題為微處理器的生產測試技術,目標為在不使用(或儘量避免使 用)可測試性設計電路(DfT, Design-for-Test)的前題下,達到預設的結構性錯誤涵蓋 率(structural fault coverage)。計劃第一年的主要成果包括:(1)蒐集並研究微處理機 測試的相關研究成果,(2)以Parwan Processor 為待測CPU,研究產生測試程式的技術, 獲得不錯的成果,與(3)蒐集並分析其他較複雜的微處理器核心,作為後續研究的 待測CPU。 Microprocessors plan a very important role in the modern microelectronics industry. In addition to serving as the central processing unit (CPU) in desktop computers, notebooks, or workstations, microprocessors are often utilized as the main control unit of many electronics products. Since the introduction of Intel 4004, microprocessors have advanced substantially in terms of the chip area, performance, and circuit/functionality complexity. All these improvements pose severe challenges on not only design verification, but also manufacturing testing. The purpose of this project is to develop microprocessor manufacturing techniques which can achieve the desired structural fault coverage without or with the least amount of DfT (Design-for-Test) circuitry. The main results of the first year include (1) collecting and studying microprocessor testing related papers and research results, (2) development of test program for the Parwan Processor and achieve acceptable structural fault coverage, and (3) collecting and analyzing publicly available processor cores for further research and study. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/19985 | 其他識別: | 912215E002040 | Rights: | 國立臺灣大學電子工程學研究所 |
顯示於: | 電子工程學研究所 |
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912215E002040.pdf | 43.34 kB | Adobe PDF | 檢視/開啟 |
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