https://scholars.lib.ntu.edu.tw/handle/123456789/173598
標題: | A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor | 作者: | Wang, Le Upadhyaya, P. Sun, Pinping Zhang, Yang Heo, Deukhyoun YI-JAN EMERY CHEN Jeong, DongHo |
公開日期: | 2006 | 起(迄)頁: | 3237-3240 | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 摘要: | This paper presents a new harmonic filtering technique to lower the phase noise of CMOS LC voltage-controlled oscillator (VCO) based on loaded-Q improvement approach. A single resistor was used at the drain node of the bias transistor instead of extra inductors and capacitors. The wide-band nature of resistance can suppress the second harmonic as well as other even harmonics leaking from the LC tank across the full period of oscillation, thus preserve the loaded quality factor of the LC tank As a proof of concept, a completely integrated 5.3GHz all PMOS LC VCO was implemented in a 0.18μm BiCMOS process. The simulation result shows the achieved phase noise of -129.5 dBc/Hz at 1-MHz offset and -110 dBc/Hz at 100-KHz offset and -86 dBc/Hz at 10-KHz while the VCO core draws 5mA from a 1.8V supply. The circuit is being fabricated with Jazz semiconductor. © 2006 IEEE. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/245564 http://ntur.lib.ntu.edu.tw/bitstream/246246/245564/-1/25.pdf https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547354398&partnerID=40&md5=b110708a555fbb77fd17a8d5cb7bdded |
ISSN: | 02714310 | SDG/關鍵字: | Bias transistor; Jazz semiconductor; Loaded-Q improvement; Bias currents; Harmonic analysis; Resistors; Variable frequency oscillators; Phase noise |
顯示於: | 電子工程學研究所 |
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