https://scholars.lib.ntu.edu.tw/handle/123456789/173851
標題: | 子計畫二:時序就是一切:論電源震盪,雜訊,及溫度對時序
之影響(1/3) Timing is Everything: Power Delivery, Signal Integrity, and Temperature (1/3) |
作者: | 陳中平 | 公開日期: | 31-十月-2004 | 出版社: | 臺北市:國立臺灣大學電子工程學研究所 | 摘要: | Due to coupling noises, process avariations, and power delivery fluctuations, design uncertainties of on-chip global interconnect systems rise sharply with deep-sub-micron (DSM) technology. It is increasingly difficult to assume deterministic and error-free signal transmission over global wires. Instead, on-chip global interconnect wires must be analyzed as an errorprone communication channel characterized by probability of bit error, and statistical timing distributions. In this paper, a novel statistical timing analysis approach is developed to analyze the behavior of two practically important pipelined multiple clock-cycle global interconnect architectures, namely, the flipflop inserted global wire and the latch inserted global wire. We present analytical formula that are based on parameters obtained using Monto Carlo simulation. These results enable a global interconnect designer to explore design trade-offs between clock frequency and probabilty of bit-error during data transmission, and to evaluate cost-effectiveness of reliability enhancement measures such as bus coding. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/20028 | 其他識別: | 922220E002019 | Rights: | 國立臺灣大學電子工程學研究所 |
顯示於: | 電子工程學研究所 |
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922220E002019.pdf | 100.71 kB | Adobe PDF | 檢視/開啟 |
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