dc.relation.reference | 第1章
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第2章
[2.1] K. S. Krisch, J. D. Bude, and L. Manchanda, “Gate Capacitance Attenuation in MOS Devices with Thin Gate Dielectrics,” IEEE Electron Device Letters, Vol. 17, NO. 11, November 1996.
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[2.3] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “Modeling of Parasitic Capacitances in Deep Submicrometer Conventional and High-K Dielectric MOS Transistors,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 959-966, April 2003.
第3章
[3.1] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L. Hebert, R. Garcia, R.Hegde, J. Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, B. Nguyen, and P. Tobin, “80nm Poly-Si Gate CMOS with HfO2 Gate Dielectric, “ IEDM Digest, pp. 651-654, 2002.
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[3.6] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “Modeling of Parasitic Capacitances in Deep Submicrometer Conventional and High-K Dielectric MOS Transistors,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 959-966, April 2003.
[3.7] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance,” IEEE Trans. Electron Devices, Vol. 49, NO. 5, pp. 826-831, May 2002.
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[3.9] C. H. Choi, Y. Wu, J. S. Goo, Z. Yu, R. W. Dutton, “Capacitance Reconstruction from Measured C-V in High Leakage Nitride/Oxide MOS,” IEEE Trans. Electron Devices, Vol. 47, NO. 10, pp. 1843-1850, Oct. 2000.
[3.10] Y. C. Yeo, T. J. King, and C. Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 1027-1035, April 2003.
[3.11] D. E. Ward and R. W. Dutton, “A Charge-Oriented Model for MOS Transistor Capacitance,” IEEE J. Solid-State Circuits, Vol. 13, NO. 5, pp. 703-708, Oct 1978.
第4章
[4.1] C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. voorde, D. Vook, C. H. Diaz, “MOS C-V Characterization of Ultrathin Gate Oxide Thickness (1.3-1.8nm)”, IEEE Elec. Dev. Letters, Vol 20, NO. 6, pp. 292-294, June 1999.
[4.2] C. H. Choi, Y. Wu, J. S. Goo, Z. Yu, R. W. Dutton, “Capacitance Reconstruction from Measured C-V in High Leakage Nitride/Oxide MOS,” IEEE Trans. Electron Devices, Vol. 47, NO. 10, pp. 1843-1850, Oct. 2000.
[4.3] KWOK K. NG and RUICHEN LIU, “On the Calculation of Specific Contact Resistivity on <100> Si,” IEEE Trans. Electron Devices, Vol. 37, NO. 6, June 1990.
[4.4] C. L. Hinkle, C. Fulton, R.J. Nemanich, and G. Lucovsky, ”Resonant tunneling in stacked dielectrics: a novel approach for obtaining the electron tunneling mass-conduction band offset energy products for advanced gate dielectrics,” Tokyo, IWGI 2003.
[4.5] Y. C. Yeo, T. J. King, and C. Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 1027-1035, April 2003.
[4.6] H.–S. P. Wong, “Beyond the conventional transistor,” IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
第5章
[5.1] Prashant Pandey, B. B. Pal, and S. Jit, “A New 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Si-SOI MESFETs,” IEEE Trans. Electron Devices, pp. 246-254, Feb. 2004.
[5.2] N. R. Mohapatra, M. P. Desai, and V. R. Rao, “Detail Analysis of FIBL in MOS Transistor with High-K Gate Dielectrics,” IEEE Proceedings of the 16th International Conference on VLSI Design, 2003.
[5.3] H.–S. P. Wong, “Beyond the conventional transistor,” IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[5.4] N. R. Mohapatra, A. Dutta, M. P. Desai, and V. R. Rao,” Effect of Fringing Capacitance in Sub 100nm MOSFET’s with High-K Gate Dielectrics,” VLSI Design, 14th International Conference on 3-7, pp. 479 – 482, Jan. 2001.
[5.5] G. C. Y. Yeap, S. Kirishnan, and M. R. Lin, “Fringing-Induced Barrier Lowering(FIBL) in Sub-100nm MOSFETs with High-K Gate Dielectrics, “Electronics Letters, pp. 1150-1152, May 1998.
[5.6] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, Johannes M. C. Stork, Z. Yu, Peter M. Zeitzoff, and Jason C. S. Woo, ”The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s, “ IEEE Trans. Electron Devices, pp. 1537-1544, July 1999.
[5.7] B. Y. Tsui and L. F. Chin, “A Comprehensive Study on the FIBL of Nanoscale MOSFETs, “ IEEE Trans. Electron Devices, pp. 1733-1735, Oct. 2004.
[5.8] S. C. Lin and J. B. Kuo, “Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure, “IEEE Trans. Electron Devices, pp. 2559-2564, Dec. 2003.
[5.9] S. C. Lin and J. B. Kuo, “Fringing-Induced Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer, “ SOI Conf. Proc., pp.93-94, Oct. 2002. | en |