https://scholars.lib.ntu.edu.tw/handle/123456789/174360
標題: | H.264移動估測器之設計與製作 Design and Implementation of an H.264 Motion Estimator |
作者: | 鄭合詞 Jheng, He-Cih |
關鍵字: | h.264 | 公開日期: | 2005 | 摘要: | H.264/MPEG-4 AVC 是新一代的視訊壓縮標準。它提供了更強大的壓縮技術,目標是取代目前既有的視訊標準。它採用了許多不同以往的技術,將壓縮效能再次提升。 在視訊壓縮標準中,移動估測技術是一個重要的單元。藉由此單元的運作,可以消除時序上重複的資料 (Temporal Redundancy),而達到有效的壓縮。再者,H.264/MPEG-4 AVC在移動估測單元上,亦做了些技術上的提升。與傳統的區塊比對移動估測相比,H.264/MPEG-4 AVC支援7種形式的區塊大小 (16 16,16 8,8 16,8 8,8 4,4 8,4 4),因此會產生41種不同相對應的移動向量。也因為將移動向量細分成如此多種的形式,更可以有效的降低資料傳輸量,提升工作頻率。 在此論文中,我們設計並實現一個一維的全區域搜索移動估測器。採用傳統常見的一維陣列 (1-D 16-PE array)架構,設計並修改內部的電路,以及主要的架構-處理單元。設計的基本概念為,重複使用較小4 4的區塊,累加出較大的8 8,8 16,16 8,和16 16區塊。傳統的一維陣列 (1-D 16-PE array)架構,計算完畢一個16 16區塊大小的移動向量,大致需要256 16個時脈週期。而此設計可以在相同的時脈週期,即256 16個時脈週期,算出41種H.264/MPEG-4 AVC所支援的移動估測向量。此外,本設計為了加快晶片的運作速度,採用管線化的設計,藉此提升效能。 利用TSMC 0.18 μm 1P6M 技術完成的H.264 畫面移動估測器,可適用於標準電視畫質的視訊。若針對CIF格式 (352 288)的圖片而言,則此晶片每秒可以處理接近123張影像。此晶片使用了約202K的邏輯閘數目,正常工作頻率為200MHz,晶片大小為 2.3 2.3 。 H.264/AVC [1][2] is the latest international video coding standard developed by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. It can achieve higher coding efficiency than these previous standards such as MPEG-4 and H.263. With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in the area of variable block searching motion estimation (VBSME), are increasing. However, AVC requires a much higher computational complexity due to the use of variable block-size motion estimation and mode decision. This has led to research into suitable flexible hardware architectures to perform the various types of VBSME. In this Thesis, we design and implement a 1-D VLSI architecture for full-search variable block size motion estimation (FSVBSME). The variable block size, sum of absolute differences (SAD) computation is performed by reusing the results of smaller sub-block computations. These are permuted and combined by incorporating a shuffling mechanism within each processing element (PE). Whereas a conventional 1-D architecture can process only one motion vector, this architecture can process up to 41 sub-blocks of motion vectors (MV) (within a macroblock) in a comparable number, 256 clock cycles. Although some relevant algorithms for motion estimation have been developed, we decide to implement a full search algorithm for block matching-based motion estimation due to its regularity and precision. The full search algorithm is suitable for hardware-oriented architecture and implementation. To achieve high efficiency or real-time application, it is important to use parallel processing elements (PE) in a motion estimation architecture. Besides, the trade-off between low-power constraint and small-area requirement is also a challenge. As a result, we adopt a 1-D array BSME architecture to implement our motion estimator. The final performance of this chip is 200MHz with a power consumption of 302 mW under 1.8V power supply, and the frames that this chip can process are 123 fps with the CIF size (352x288). This prototype chip of H.264/MPEG-4 AVC Motion Estimation System is realized in TSMC 0.18μm 1P6M technology and using Artisan 0.18μm standard CMOS cell library via CIC. And this chip also includes test consideration. The total gate count is about 202 K and die size is 2.3x2.3 including two on-chip memories. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57596 | 其他識別: | en-US |
顯示於: | 電子工程學研究所 |
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ntu-94-R92943100-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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