https://scholars.lib.ntu.edu.tw/handle/123456789/175273
標題: | 高速與低功耗之類比數位轉換器設計 Design of High-Speed and Low-Power Analog-to-Digital Converters |
作者: | 林晉宇 Lin, Chin-Yu |
關鍵字: | 管線式連續漸進暫存類比數位轉換器;多通道類比數位轉換器;時間偏斜校正;Pipelined-SAR ADC;Time-Interleaved ADC;timing skew calibration | 公開日期: | 2016 | 摘要: | 類比數位轉換器在現今的SoC系統中扮演關鍵的元件,因為其連接了真實世界的類比訊號與數位信號處理器。隨著近年來攜帶式裝置迅速發展,高速低功耗的類比數位轉換器需求也隨之劇增。此篇論文提出了兩種類比數位轉換器之設計,達到高速、低功率消耗等設計目標。 本論文中首先提出一個雙通道十二位元、兩億一千萬赫茲取樣率的管線式連續漸進暫存類比數位轉換器。轉換器架構上分為三級,前兩級使用了提出的被動式餘值轉移的技巧來節省功耗,後兩級則採用主動式放大來實現。提出的架構實現於六十五奈米製程中,在1伏特供應電壓下消耗5.3毫瓦。當輸入低頻信號與操作於奈奎斯頻率時,信噪失真比(SNDR)分別為63.5分貝與60.1分貝。 第二部份則是包含了應用於下一代行動通訊射頻前端系統中一個十位元、二十六億赫茲取樣率時間交錯式連續漸進暫存類比數位轉換器。論文中實現了十六通道十位元、二十六億赫茲取樣率時間交錯式連續漸進暫存類比數位轉換器,並採用差值取樣輔助型類比數位轉換器與數位混波校正技術。提出的類比數位轉換器實現於四十奈米製程中,在1.1伏特供應電壓下消耗18.4毫瓦。當操作於奈奎斯頻率時,信噪失真比(SNDR)為50.6分貝。 Analog-to-digital converter (ADC) has been recognized as one of the crucial building blocks in the modern SoC system because it provides the link between the real-world analog information and the digital signal processors (DSPs). The demand on high-speed and low-power ADCs has increased as many portable applications grow rapidly in recent years. In this dissertation, two ADCs are presented to achieve high-speed and low-power design. The first part of this dissertation demonstrates a 12-b, 210-MS/s 2-channel interleaved pipelined-SAR ADC. The proposed ADC is partitioned into 3 stages with passive residue transfer technique between the 1st and the 2nd stages for power saving and active residue amplification between the 2nd and the 3rd stages. The prototype, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at DC and 60.1 dB near Nyquist-rate. The second part present a 10-b, 2.6-GS/s time-interleaved SAR ADC for the RF front-end of the next-generation mobile system. A 16-channel time-interleaved 10-b SAR ADC, employing the proposed delta-sampling auxiliary SAR ADC and digital mixing calibration to correct timing skew error, achieves a 2.6-GS/s sampling rate. The ADC has been fabricated in a 40-nm CMOS technology and achieves a 50.6-dB SNDR at Nyquist rate while dissipating 18.4 mW from a 1.1-V power supply. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/276201 | DOI: | 10.6342/NTU201600259 | Rights: | 論文公開時間: 2026/5/24 論文使用權限: 同意有償授權(權利金給回饋學校) |
顯示於: | 電子工程學研究所 |
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ntu-105-D98943015-1.pdf | 23.32 kB | Adobe PDF | 檢視/開啟 |
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