https://scholars.lib.ntu.edu.tw/handle/123456789/301446
標題: | Architecture design for deblocking filter in H.264/JVT/AVC | 作者: | Huang, Y.-W. Chen, T.-W. Hsieh, B.-Y. Wang, T.-C. Chang, T.-H. LIANG-GEE CHEN |
公開日期: | 2003 | 卷: | 1 | 起(迄)頁: | I693 - I696 | 來源出版物: | Proceedings - IEEE International Conference on Multimedia and Expo | 會議論文: | 2003 International Conference on Multimedia and Expo, ICME 2003 | 摘要: | This paper presents an efficient VLSI architecture for the deblocking filter in H.264/JVT/AVC. We use an array of 8 × 48-bit shift registers with reconfigurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 μm technology, the synthesized logic gate count is only 19.1 K (not including a 96 × 32 SRAM and a 64 × 32 SRAM) when the maximum frequency is 100 MHz. Our architecture design can easily support real-time deblocking of 720p (1280 × 720) 30 Hz video. It is valuable for platform-based design of H.264 codec. © 2003 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84908483284&doi=10.1109%2fICME.2003.1221012&partnerID=40&md5=2419783bdbc5d01e53a1bba68258af6a http://scholars.lib.ntu.edu.tw/handle/123456789/301446 |
ISSN: | 19457871 | DOI: | 10.1109/ICME.2003.1221012 | SDG/關鍵字: | Design; Shift registers; Static random access storage; Architecture designs; Deblocking filters; Maximum frequency; Platform based design; Real-time deblocking; Reconfigurable; SRAM module; VLSI architectures; Digital storage |
顯示於: | 電機工程學系 |
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
01221012.pdf | 285.61 kB | Adobe PDF | 檢視/開啟 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。