|Title:||A novel high speed asynchronous scalable variable-length self-routing packet switch||Authors:||Wang, T.-Y.
|Keywords:||Centralized control; Circuit simulation; Ethernet networks; Field programmable gate arrays; Packet switching; Routing protocols; Switches; Switching circuits; Throughput; Traffic control||Issue Date:||2003||Journal Volume:||3||Start page/Pages:||1181-1189||Source:||APCC 2003 - 9th Asia-Pacific Conference on Communications, in conjunction with 6th Malaysia International Conference on Communications, MICC 2003||Abstract:||
In this paper, we propose a novel high-speed asynchronous scalable variable-length self-routing packet switch, called NTU-II switch. The architecture is based on a multi-plane crossbar structure with a self-routing switch element. Contrary to conventional crossbar switches, the proposed switch does not need any central controller, complex scheduling schemes, speedup mechanism, or arbiter. The routing mechanism works in each self-routing switch element independently and uses polling handshaking protocol to transfer packets between internal circuits. Therefore, the modular design, high scalability, and asynchronous transfer become possible and easier. The throughput of the proposed switch is analyzed and simulated. Owing to the sub-switch plane mechanism, the throughput of a four plane switch without input port expansion can easily reach 100% simulated in both uniform distribution input traffic and hot spot input traffic model. The architecture has been verified in 100 Mbps Ethernet system with FPGA, and completely simulated in 1 Gb/s (IEEE 802.3z) Ethernet system with FPGA (VirtexII vc2v3000fg676-4, Xilinx Corp.). Because of its simplicity and scalable design, the proposed switch also may be implemented by VLSI technology to meet the 10 Gb/s (IEEE802.3ae) Ethernet switch requirements. © 2003 IEEE.
|DOI:||10.1109/APCC.2003.1274287||SDG/Keyword:||Choppers (circuits); Circuit simulation; Complex networks; Ethernet; Integrated circuit design; Network architecture; Networks (circuits); Packet networks; Packet switching; Routing protocols; Switches; Switching circuits; Throughput; Traffic control; VLSI circuits; Centralized control; Complex scheduling; Cross-bar structures; Ethernet networks; Handshaking protocol; High scalabilities; Self-routing packets; Uniform distribution; Field programmable gate arrays (FPGA)|
|Appears in Collections:||電機工程學系|
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