https://scholars.lib.ntu.edu.tw/handle/123456789/303243
標題: | Simultaneous routing and buffering in floorplan design | 作者: | Fang, J.P. Tong, Y.-S. SAO-JIE CHEN |
關鍵字: | Buffer insertion; Floorptanning; Global routing | 公開日期: | 2003 | 卷: | 2003-January | 起(迄)頁: | 188-191 | 來源出版物: | International Symposium on VLSI Technology, Systems, and Applications | 摘要: | To deal with the floorplan design in a System-on-a-Chip (SOC), we have developed an EDA tool that simultaneuosly considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a Manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution. © 2003 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-33645748798&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/303243 |
ISSN: | 19308868 | DOI: | 10.1109/VTSA.2003.1252584 | SDG/關鍵字: | Algorithms; Application specific integrated circuits; Buffer circuits; Iterative methods; Programmable logic controllers; System-on-chip; Buffer insertion; Floor-planning; Floorplan design; Floorptanning; Global routing; Manhattan routing; Processing speed; System on a chip; Integrated circuit design |
顯示於: | 電機工程學系 |
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01252584.pdf | 307.24 kB | Adobe PDF | 檢視/開啟 |
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