https://scholars.lib.ntu.edu.tw/handle/123456789/309232
標題: | Fast Postplacement Optimization Using Functional Symmetries | 作者: | Chang, C.-W. Hsiao, M.-F. Hu, B. Wang, K. Marek-Sadowska, M. Cheng, C.-K. SAO-JIE CHEN |
關鍵字: | Functional symmetry; Logic restructuring; Logic synthesis; Physical synthesis; Postlayout optimization; Timing closure | 公開日期: | 2004 | 卷: | 23 | 期: | 1 | 起(迄)頁: | 102-118 | 來源出版物: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 摘要: | The timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear-time algorithm is proposed to detect functional symmetries in the Boolean network which are then used as the basis for rewiring. Integration with an existing gate-sizing algorithm further proves the effectiveness of our technique. Three applications are demonstrated: delay, power, and reliability optimization. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-0346500594&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/309232 |
ISSN: | 02780070 | DOI: | 10.1109/TCAD.2003.819904 | SDG/關鍵字: | Algorithms; Boolean functions; Computer aided design; Graph theory; Hot carriers; Kinetic energy; Optimization; Perturbation techniques; Transconductance; Transistors; Functional symmetries; Logic restructuring; Logic synthesis; Physical synthesis; Postlayout optimization; Timing closure; Integrated circuits |
顯示於: | 電機工程學系 |
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