https://scholars.lib.ntu.edu.tw/handle/123456789/313904
標題: | Memory efficient JPEG 2000 architecture with stripe pipeline scheme | 作者: | Fang, H.-C. Chang, Y.-W. Cheng, C.-C. Chen, C.-C. LIANG-GEE CHEN |
公開日期: | 2005 | 卷: | V | 起(迄)頁: | V1-V4 | 來源出版物: | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | 會議論文: | 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05 | 摘要: | Memory issue is the most critical problem for a high performance JPEG 2000 architecture. The tile memory occupies more than 50% of area in conventional JPEG 2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a Level Switch Discrete Wavelet Transform (LS-DWT) and a Code-block Switch Embedded Block Coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an inter-leaved scheme. As a result of above techniques, the overall memory requirements of the proposed architecture can be reduced to only 8.5% comparing with conventional architectures. © 2005 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-33646755881&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/313904 |
ISSN: | 15206149 | DOI: | 10.1109/ICASSP.2005.1416225 | SDG/關鍵字: | Data storage equipment; Embedded systems; Pipeline processing systems; Problem solving; Signal encoding; Wavelet transforms; Embedded Block Coding; Level Switch Discrete Wavelet Transform (LS-DWT); Memory efficient JPEG 2000 architecture; Stripe pipeline scheme; Computer architecture |
顯示於: | 電機工程學系 |
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
01416225.pdf | 592.77 kB | Adobe PDF | 檢視/開啟 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。