https://scholars.lib.ntu.edu.tw/handle/123456789/313919
標題: | Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos | 作者: | Chen, T.-W. Huang, Y.-W. Chen, T.-C. Chen, Y.-H. Tsai, C.-Y. LIANG-GEE CHEN |
公開日期: | 2005 | 起(迄)頁: | 2931-2934 | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 會議論文: | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 | 摘要: | The most critical issue of an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of parallelism. In this paper, a hybrid task pipelining scheme is first presented to greatly reduce the internal memory size and bandwidth. Block-level, macroblocklevel, and macroblock/frame-level pipelining schedules are arranged for CAVLD/IQ/IT/INTRA PRED, INTER PRED, and DEBLOCK, respectively. Appropriate degrees of parallelism for each pipeline task are also proposed. Moreover, efficient modules are contributed. The CAVLD unit smoothly decodes bitstream into symbols without bubble cycles. The INTER PRED unit highly exploits the data reuse between interpolation windows of neighboring blocks to save 60% of external memory bandwidth. DEBLOCK unit doubles the processing capability of our previous work with only 35.3% of logic gate count overhead. The proposed baseline profile decoder architecture can support up to 2048×1024 30fps videos with 217K logic gates, 10KB SRAMs, and 528.9MB/s bus bandwidth when operating at 120MHz. © 2005 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-67649092274&doi=10.1109%2fISCAS.2005.1465241&partnerID=40&md5=449cdeca27b6cc34e4867fca4ac040aa http://scholars.lib.ntu.edu.tw/handle/123456789/313919 |
ISSN: | 02714310 | DOI: | 10.1109/ISCAS.2005.1465241 | SDG/關鍵字: | Architecture designs; Baseline profiles; Bit stream; Bus bandwidth; Critical issues; Data reuse; Decoder architecture; External memory; H.264/AVC decoders; High definition video; Hybrid tasks; Internal memory; Macroblock-level; Processing capability; System architecture design; Bandwidth; Decoding; Logic gates; Motion compensation; Motion Picture Experts Group standards; Architectural design |
顯示於: | 電機工程學系 |
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01465241.pdf | 100.96 kB | Adobe PDF | 檢視/開啟 |
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