https://scholars.lib.ntu.edu.tw/handle/123456789/318052
標題: | Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis | 作者: | Rong Jiang Wenyin Fu Janet Meiling Wang CHUNG-PING CHEN |
關鍵字: | Capacitance; Parasitic extraction; Principle factor analysis; Process variations; Random variable reduction | 公開日期: | 十一月-2005 | 來源出版物: | ICCAD | 摘要: | Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy. ©2005 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/318052 https://www.scopus.com/inward/record.uri?eid=2-s2.0-33751418350&doi=10.1109%2fICCAD.2005.1560153&partnerID=40&md5=ba3878d1bbe79b66ed2bbb53a5eb05fa |
DOI: | 10.1109/ICCAD.2005.1560153 | SDG/關鍵字: | Large scale systems; Mathematical models; Random processes; Statistical methods; Systems analysis; WSI circuits; Capacitance model; Parasitic extraction; Principle factor analysis; Random variable reduction; VLSI circuits |
顯示於: | 電子工程學研究所 |
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