https://scholars.lib.ntu.edu.tw/handle/123456789/323973
標題: | An enhanced BSA for floorplanning | 作者: | Fang, J.P. Tong, Y.-S. SAO-JIE CHEN |
關鍵字: | Buffer insertion; Dominant wide bus; Floorplanning; Routing | 公開日期: | 2006 | 卷: | E89-A | 期: | 2 | 起(迄)頁: | 528-534 | 來源出版物: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 摘要: | In the floorplan design of System-on-Chip (SOC), Buffer Site Approach (BSA) has been used to relax the buffer congestion problem. However, for a floorplan with dominant wide bus, BSA may instead worsen the congestion. Our proposed Enhanced Buffer Site Approach (EBSA) extends existing BSA in a way that buffers of dominant wide bus can be distributed more evenly while reserving the same fast operation speed as BSA does. Experiments have been performed to integrate our model into an iterative floorplanning algorithm, and the results reveal that buffer congestion in a floorplan with dominant wide bus can be much abated. Copyright © 2006 The Institute of Eletronics, Information and Communication Engineers. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-33645749898&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/323973 |
ISSN: | 09168508 | DOI: | 10.1093/ietfec/e89-a.2.528 | SDG/關鍵字: | Algorithms; Congestion control (communication); Floors; Mathematical models; Problem solving; Buffer insertion; Dominant wide bus; Floorplanning; Routing; Integrated circuits |
顯示於: | 電機工程學系 |
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