https://scholars.lib.ntu.edu.tw/handle/123456789/324048
標題: | Voltage Island aware floorplanning for power and timing optimization | 作者: | Lee, W.-P. Liu, H.-Y. Chang, Y.-W. YAO-WEN CHANG |
公開日期: | 2006 | 起(迄)頁: | 389-394 | 來源出版物: | IEEE/ACM International Conference on Computer-Aided Design | 摘要: | Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints. Copyright 2006 ACM. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-43349099463&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/324048 |
DOI: | 10.1109/ICCAD.2006.320063 | SDG/關鍵字: | Design; Dynamic programming; Electric power utilization; Integrated circuit layout; Integrated circuits; Mathematical programming; Optimization; Systems engineering; Time measurement; Timing circuits; chip designs; Computer-aided design; Effective voltage; Experimental results; Floor-planning; Floorplanner; international conferences; level shifters; Multiple supply voltages; Net list; Optimal solutions; Power consumption (CE); Power consumption reduction; Power savings; Timing constraints; Timing optimization; Voltage assignments; voltage domains; voltage islands; Energy conservation |
顯示於: | 電子工程學研究所 |
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