https://scholars.lib.ntu.edu.tw/handle/123456789/324050
標題: | RLC coupling-aware simulation and on-chip bus encoding for delay reduction | 作者: | Tu, S.-W. Jou, J.-Y. YAO-WEN CHANG |
關鍵字: | Bus-invert method; Coupling; Inductance; Interconnect delay; Worst case switching pattern | 公開日期: | 2006 | 卷: | 25 | 期: | 10 | 起(迄)頁: | 2258-2264 | 來源出版物: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 摘要: | This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses. © 2006 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-33748302173&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/324050 |
ISSN: | 02780070 | DOI: | 10.1109/TCAD.2005.860956 | SDG/關鍵字: | Capacitance; Computer simulation; Delay circuits; Electric resistance; Encoding (symbols); Inductance; Mathematical models; Microprocessor chips; Switching theory; Bus-invert method; Inductance-dominated buses; Interconnect delay; Worst case switching pattern; Coupled circuits |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。