https://scholars.lib.ntu.edu.tw/handle/123456789/325484
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsiang-Hui Chang | en_US |
dc.contributor.author | Jung-Yu Chang | en_US |
dc.contributor.author | Chun-Yi Kuo | en_US |
dc.contributor.author | SHEN-IUAN LIU | - |
dc.creator | Hsiang-Hui Chang;Jung-Yu Chang;Chun-Yi Kuo;Shen-Iuan Liu | - |
dc.date.accessioned | 2018-09-10T06:02:32Z | - |
dc.date.available | 2018-09-10T06:02:32Z | - |
dc.date.issued | 2006-05 | - |
dc.identifier.issn | 00189200 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/325484 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33646421401&doi=10.1109%2fJSSC.2006.874036&partnerID=40&md5=4f26fc884f90c6504b8e84183ffdcb3e | - |
dc.description.abstract | A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature, operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-μm CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9 ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree). © 2006 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits | en_US |
dc.source | AH-anncc | - |
dc.subject | Calibration; Delay-locked loop (DLL); Multiphase | - |
dc.subject.other | Delay-locked loop (DLL); Digital calibration circuits; Multiphase; Power dissipations; CMOS integrated circuits; Electric potential; Error analysis; Natural frequencies; Thermal effects; Calibration | - |
dc.title | A 0.7-2-GHz self-calibrated multiphase delay-locked loop | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/jssc.2006.874036 | - |
dc.identifier.scopus | 2-s2.0-33646421401 | - |
dc.identifier.isi | WOS:000237210500006 | - |
dc.relation.pages | 1051-1061 | - |
dc.relation.journalvolume | 41 | - |
dc.relation.journalissue | 5 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-3765-2948 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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