https://scholars.lib.ntu.edu.tw/handle/123456789/325750
標題: | On-chip random jitter testing using low tap-count coarse delay lines | 作者: | JIUN-LANG HUANG | 關鍵字: | Analog/mixed-signal testing; Design-for-test; Jitter measurement; Random jitter | 公開日期: | 十二月-2006 | 卷: | 22 | 期: | 4-6 | 起(迄)頁: | 387 - 398 | 來源出版物: | Journal of Electronic Testing: Theory and Applications (JETTA) | 摘要: | An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations. © Springer Science + Business Media, LLC 2006. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/325750 https://www.scopus.com/inward/record.uri?eid=2-s2.0-33846682693&doi=10.1007%2fs10836-006-9444-3&partnerID=40&md5=b96497a1e7a6f7cff289091249e5827e |
ISSN: | 09238174 | DOI: | 10.1007/s10836-006-9444-3 | SDG/關鍵字: | Computer simulation; Design for testability; Electric delay lines; Microprocessor chips; Probability; Probability density function; Analog/mixed signal testing; Delay line value deviations; Jitter measurement; Random jitters; Jitter |
顯示於: | 電子工程學研究所 |
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