https://scholars.lib.ntu.edu.tw/handle/123456789/332263
標題: | X-route: An x-architecture full-chip multilevel router | 作者: | Chang, C.-F. Chang, Y.-W. YAO-WEN CHANG |
公開日期: | 2007 | 起(迄)頁: | 229-232 | 來源出版物: | 20th Anniversary IEEE International SOC Conference | 摘要: | In this paper, we present an X-architecture multilevel full-chip router, called X-Route. Unlike the traditional Λ-shaped multilevel framework that adopts bottom-up coarsening followed by top-down uncoarsening, our multilevel framework runs in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. The top-down uncoarsening stage performs octagonal global routing and X-detailed routing for local nets at each level and then refines the solution for the next level. Then, the bottom-up coarsening stage performs the X-detailed routing to reroute failed nets and refines the solution level by level. Since we perform top-down routing first, global long nets are routed earlier. To prevent a wrong decision from blocking the later nets, we keep a dynamic congestion map that records the updated routing congestion information based on the routed nets and the global-path prediction of the unrouted nets. To take full advantage of the X-architecture, we also develop a progressive X-Steiner tree algorithm based on the delaunay triangulation approach for the X-architecture. Compared with the state-of-the-art Λ-shaped multilevel routing for the X-architecture, experimental results show that our X-Route reduces the respective wirelength and average delay by about 14.05% and 30.62%, with better routing completion. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-51049110706&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/332263 |
DOI: | 10.1109/SOCC.2007.4545464 | SDG/關鍵字: | Architecture; Coarsening; Marine biology; Programmable logic controllers; Refining; Routing algorithms; X-architecture; Computer networks; Algorithms; Controllers; Fineness; Refining |
顯示於: | 電子工程學研究所 |
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