https://scholars.lib.ntu.edu.tw/handle/123456789/332263
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, C.-F. | en_US |
dc.contributor.author | Chang, Y.-W. | en_US |
dc.contributor.author | YAO-WEN CHANG | zz |
dc.creator | Chang, C.-F.;Chang, Y.-W. | - |
dc.date.accessioned | 2018-09-10T06:30:58Z | - |
dc.date.available | 2018-09-10T06:30:58Z | - |
dc.date.issued | 2007 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-51049110706&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/332263 | - |
dc.description.abstract | In this paper, we present an X-architecture multilevel full-chip router, called X-Route. Unlike the traditional Λ-shaped multilevel framework that adopts bottom-up coarsening followed by top-down uncoarsening, our multilevel framework runs in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. The top-down uncoarsening stage performs octagonal global routing and X-detailed routing for local nets at each level and then refines the solution for the next level. Then, the bottom-up coarsening stage performs the X-detailed routing to reroute failed nets and refines the solution level by level. Since we perform top-down routing first, global long nets are routed earlier. To prevent a wrong decision from blocking the later nets, we keep a dynamic congestion map that records the updated routing congestion information based on the routed nets and the global-path prediction of the unrouted nets. To take full advantage of the X-architecture, we also develop a progressive X-Steiner tree algorithm based on the delaunay triangulation approach for the X-architecture. Compared with the state-of-the-art Λ-shaped multilevel routing for the X-architecture, experimental results show that our X-Route reduces the respective wirelength and average delay by about 14.05% and 30.62%, with better routing completion. | - |
dc.language | en | en |
dc.relation.ispartof | 20th Anniversary IEEE International SOC Conference | en_US |
dc.source | AH-Scopus to ORCID | - |
dc.subject.classification | [SDGs]SDG14 | - |
dc.subject.other | Architecture; Coarsening; Marine biology; Programmable logic controllers; Refining; Routing algorithms; X-architecture; Computer networks; Algorithms; Controllers; Fineness; Refining | - |
dc.title | X-route: An x-architecture full-chip multilevel router | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/SOCC.2007.4545464 | - |
dc.identifier.scopus | 2-s2.0-51049110706 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 229-232 | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
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