https://scholars.lib.ntu.edu.tw/handle/123456789/334022
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Y.-J. Lai | en_US |
dc.contributor.author | TSUNG-HSIEN LIN | - |
dc.creator | T.-H. Lin;Y.-J. Lai | - |
dc.date.accessioned | 2018-09-10T06:37:55Z | - |
dc.date.available | 2018-09-10T06:37:55Z | - |
dc.date.issued | 2007-02 | - |
dc.identifier.issn | 00189200 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/334022 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33847730295&doi=10.1109%2fJSSC.2006.889360&partnerID=40&md5=ac7bbd21c55c024c3156671160b27445 | - |
dc.description.abstract | This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-μm CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4 μs. © 2007 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits | en_US |
dc.source | AH-anncc | - |
dc.subject | Calibration; CMOS integrated circuits; Frequency synthesizer; Period-based frequency comparison; Phase detector; Phase-locked loop (PLL); Voltage-controlled oscillator (VCO) | - |
dc.subject.other | Frequency synthesizer; Period-based frequency comparison; Phase detectors; Acoustic noise; Bandwidth; Calibration; CMOS integrated circuits; Natural frequencies; Phase locked loops; Variable frequency oscillators | - |
dc.title | An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/JSSC.2006.889360 | - |
dc.identifier.scopus | 2-s2.0-33847730295 | - |
dc.relation.pages | 340-349 | - |
dc.relation.journalvolume | 42 | - |
dc.relation.journalissue | 2 | - |
item.fulltext | no fulltext | - |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | none | - |
item.openairetype | journal article | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-1733-5945 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。