https://scholars.lib.ntu.edu.tw/handle/123456789/341025
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, T.-C. | en_US |
dc.contributor.author | Jiang, Z.-W. | en_US |
dc.contributor.author | Hsu, T.-C. | en_US |
dc.contributor.author | Chen, H.-C. | en_US |
dc.contributor.author | YAO-WEN CHANG | - |
dc.creator | Chen, T.-C.;Jiang, Z.-W.;Hsu, T.-C.;Chen, H.-C.;Chang, Y.-W. | - |
dc.date.accessioned | 2018-09-10T07:03:48Z | - |
dc.date.available | 2018-09-10T07:03:48Z | - |
dc.date.issued | 2008 | - |
dc.identifier.issn | 02780070 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-45849140142&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/341025 | - |
dc.description.abstract | In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor et al. and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results. © 2008 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | en_US |
dc.source | AH-Scopus to ORCID | - |
dc.subject | Legalization (LG); Physical design; Placement | - |
dc.subject.other | Conjugate gradient method; Analytical Placement; Density constraints; Gaussian smoothing; Legalization (LG); Physical design; Placement; Smoothing techniques; Step-size controls; Placers | - |
dc.title | NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints | - |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TCAD.2008.923063 | - |
dc.identifier.scopus | 2-s2.0-45849140142 | - |
dc.identifier.isi | WOS:000257239100006 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 1228-1240 | - |
dc.relation.journalvolume | 27 | - |
dc.relation.journalissue | 7 | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | open | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。