https://scholars.lib.ntu.edu.tw/handle/123456789/350347| Title: | Voltage-island partitioning and floorplanning under timing constraints | Authors: | Lee, W.-P. Liu, H.-Y. Chang, Y.-W. YAO-WEN CHANG |
Issue Date: | 2009 | Journal Volume: | 28 | Journal Issue: | 5 | Start page/Pages: | 690-702 | Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-65349085671&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/350347 |
DOI: | 10.1109/TCAD.2009.2013997 |
| Appears in Collections: | 電子工程學研究所 |
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