https://scholars.lib.ntu.edu.tw/handle/123456789/350371
標題: | A novel wire-density-driven full-chip routing system for cmp variation control | 作者: | Chen, H.-Y. Chou, S.-J. Wang, S.-L. YAO-WEN CHANG |
關鍵字: | Design for manufacturability; Layout; Physical design; Routing | 公開日期: | 2009 | 卷: | 28 | 期: | 1 | 起(迄)頁: | 193-206 | 來源出版物: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 摘要: | As nanometer technology advances, the post chemicalmechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following time-consuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works. © 2006 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-59049090040&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/350371 |
ISSN: | 02780070 | DOI: | 10.1109/TCAD.2008.2009156 | SDG/關鍵字: | Design; Machine design; Nanotechnology; Optical instruments; A densities; Art works; Chemical-mechanical polishing; Critical area analysis; Delaunay triangulations; Density uniformities; Design for manufacturability; Full-chip routing; Grid-based routing; Input datum; Interconnect performance; Intermediate stages; Layout; Nanometer technologies; Physical design; Planarity; Planarization; Reticle enhancement techniques; Routing; Routing frameworks; Side effects; Top downs; Voronoi diagrams; Wire |
顯示於: | 電子工程學研究所 |
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