https://scholars.lib.ntu.edu.tw/handle/123456789/350718
標題: | Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder | 作者: | AN-YEU(ANDY) WU Lin, C.-H. Chen, C.-Y. Wu, A.-Y. Tsai, T.-H. AN-YEU(ANDY) WU |
關鍵字: | Low-power design; Maximum a posteriori (MAP) algorithm; Turbo decoder | 公開日期: | 2009 | 卷: | 56 | 期: | 5 | 起(迄)頁: | 1005-1016 | 來源出版物: | IEEE Transactions on Circuits and Systems I: Regular Papers | 摘要: | Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2 × 2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2 × 2 traceback structure is implemented by using a 0.13-μm CMOS process in a core area of 7.16 mm2. Based on postlayout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration. © 2009 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-67649297996&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/350718 |
DOI: | 10.1109/TCSI.2009.2017118 | SDG/關鍵字: | Cache memory; Convolution; Electric power supplies to apparatus; Electric power utilization; Energy efficiency; Genetic algorithms; Turbo codes; Wimax; Convolutional turbo codes; Low-power design; Low-power memory; Maximum a posteriori algorithm; Maximum through-put; Operating frequency; Post layout simulation; Turbo decoders; Iterative decoding |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。