https://scholars.lib.ntu.edu.tw/handle/123456789/359586
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHIEN-MO LI | zz |
dc.contributor.author | J. Y. Wen | en_US |
dc.contributor.author | CHIEN-MO LI | en_US |
dc.date.accessioned | 2018-09-10T08:19:10Z | - |
dc.date.available | 2018-09-10T08:19:10Z | - |
dc.date.issued | 2010-01 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/359586 | - |
dc.language | en | en |
dc.source | AH-anncc | - |
dc.title | Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium | - |
dc.type | patent | en |
item.cerifentitytype | Patents | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_15cd | - |
item.openairetype | patent | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-4393-5186 | - |
crisitem.author.orcid | 0000-0002-4393-5186 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電子工程學研究所 |
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