https://scholars.lib.ntu.edu.tw/handle/123456789/365122
標題: | ReSSP: A 5.877 TOPS/W reconfigurable smart-camera stream processor | 作者: | Chan, W.-K. Tseng, Y.-H. Tsung, P.-K. Chuang, T.-D. Tsai, Y.-M. Chen, W.-Y. LIANG-GEE CHEN SHAO-YI CHIEN |
公開日期: | 2011 | 來源出版物: | Proceedings of the Custom Integrated Circuits Conference | 會議論文: | 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 | 摘要: | A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5x to 33.0x and 3.8x to 74.2x better than the state-of-the-art works, respectively. © 2011 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-80455156131&doi=10.1109%2fCICC.2011.6055296&partnerID=40&md5=c2f10ed5c3374adc697a29fac40b6883 http://scholars.lib.ntu.edu.tw/handle/123456789/365122 |
ISSN: | 08865930 | DOI: | 10.1109/CICC.2011.6055296 | SDG/關鍵字: | 90nm CMOS; Area efficiency; Power efficiency; Re-configurable; Smart-camera; Stream processing; Stream processor; Vision processing; Cameras; CMOS integrated circuits; Computer hardware description languages; Efficiency; Integrated circuit manufacture; Integrated circuits; Reconfigurable hardware |
顯示於: | 電子工程學研究所 |
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