https://scholars.lib.ntu.edu.tw/handle/123456789/366767
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Y.-T. Lin | en_US |
dc.contributor.author | J.-L. Huang | en_US |
dc.contributor.author | X. Wen | en_US |
dc.contributor.author | JIUN-LANG HUANG | zz |
dc.creator | Y.-T. Lin;J.-L. Huang;X. Wen | - |
dc.date.accessioned | 2018-09-10T08:47:22Z | - |
dc.date.available | 2018-09-10T08:47:22Z | - |
dc.date.issued | 2011-09 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/366767 | - |
dc.language | en | en |
dc.relation.ispartof | International Test Conference | en_US |
dc.source | AH-anncc | - |
dc.title | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/TEST.2011.6139132 | - |
dc.identifier.scopus | 2-s2.0-84863142459 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.fulltext | no fulltext | - |
item.cerifentitytype | Publications | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Program in Integrated Circuit Design and Automation | - |
crisitem.author.orcid | 0000-0002-9425-3855 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
Appears in Collections: | 電子工程學研究所 |
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