https://scholars.lib.ntu.edu.tw/handle/123456789/372968
標題: | Traffic-balanced topology-aware multiple routing adjustment for throttled 3D NoC systems | 作者: | AN-YEU(ANDY) WU Chen, K.-C. Lin, S.-Y. Hung, H.-S. AN-YEU(ANDY) WU |
關鍵字: | 3D IC; 3D NoC; Topology-aware adaptive routing; Transport layer assisted routing | 公開日期: | 2012 | 起(迄)頁: | 120-124 | 來源出版物: | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 摘要: | The thermal issue is important for 3D Network-on-Chip systems. To ensure the thermal safety, the near-overheat routers are throttled and the 3D topology becomes Non-Stationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, Transport Layer Assisted Routing (TLAR) scheme was proposed. It has better performance than the conventional routing approaches for NSI-Mesh. However, it still suffers significant traffic congestion in the bottom chip layer due to the insufficient lateral path diversities. To achieve more balanced traffic, we propose a Traffic-balanced Topology-aware Multiple Routing Adjustment (TTMRA). The experimental results show that the proposed TTMRA can improve 81.8% ∼ 102.3% network throughput than TLAR scheme. © 2012 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84875316229&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/372968 |
DOI: | 10.1109/SiPS.2012.13 | SDG/關鍵字: | 3D NoC; Adaptive routing; Better performance; Conventional routing; Multiple routing; Network throughput; Network-on-chip systems; Transport layers; Signal processing; Three dimensional computer graphics; Topology; Traffic congestion; VLSI circuits; Routers |
顯示於: | 電機工程學系 |
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